Datasheet

MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
8 _______________________________________________________________________________________
DIFFERENTIAL INPUT VOLTAGE DEFINITION
V
CC
V
CC
V
ILD
(MAX)
V
IHD
(MAX)
V
ILD
(MIN)
V
IHD
(MIN)
V
EE
V
EE
V
BB
V
IH
V
IL
V
IHD
- V
ILD
SINGLE-ENDED INPUT VOLTAGE DEFINITION
V
IHD
- V
ILD
Figure 1. Input Voltage Definitions
CLK
CLK
Q_
Q_
Q_ - Q_
20%
20%
80%
80%
V
IHD
- V
ILD
V
OH
- V
OL
V
OH
- V
OL
V
OH
- V
OL
DIFFERENTIAL OUTPUT WAVEFORM
0V (DIFFERENTIAL)
V
IHD
V
ILD
V
OH
V
OL
t
PLHD
t
R
t
F
t
PHLD
Figure 2. Differential Input (CLK_, CLK _) to Output (Q_, Q _) Delay Timing Diagram