Datasheet

MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
_______________________________________________________________________________________ 7
Pin Description
PIN
PLCC QFN
NAME FUNCTION
1, 8, 15, 22
4, 11, 18, 25
V
CC
Positive Supply Voltage. Bypass each V
CC
to V
EE
with 0.1µF and 0.01µF ceramic
capacitors. Place the capacitors as close to the device as possible, with the smaller
value capacitor closest to the device.
25CLK0 Inverting Differential Clock Input 0. Internal 105kΩ pulldown to V
EE
.
36V
BB
Reference Output Voltage. Connect to the inverting or noninverting clock input to
provide a reference for single-ended operation. When used, bypass V
BB
to V
CC
with a
0.01µF ceramic capacitor. Otherwise leave open.
47CLK1 Noninverting Differential Clock Input 1. Internal 105kΩ pulldown to V
EE
.
58CLK1 Inverting Differential Clock Input 1. Internal 105kΩ pulldown to V
EE
.
69N.C. Not Connected
710Q7 Inverting Q7 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
912Q7Noninverting Q7 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
10 13 Q6 Inverting Q6 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
11 14 Q6 Noninverting Q6 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
12 15 Q5 Inverting Q5 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
13 16 Q5 Noninverting Q5 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
14 17 Q4 Inverting Q4 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
16 19 Q4 Noninverting Q4 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
17 20 Q3 Inverting Q3 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
18 21 Q3 Noninverting Q3 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
19 22 Q2 Inverting Q2 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
20 23 Q2 Noninverting Q2 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
21 24 Q1 Inverting Q1 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
23 26 Q1 Noninverting Q1 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
24 27 Q0 Inverting Q0 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
25 28 Q0 Noninverting Q0 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
26 1 V
EE
Negative Supply Voltage
27 2
CLK_SEL
Clock Select Input. When driven low, the CLK0 input is selected. Drive high to select
the CLK1 Input. The CLK_SEL threshold is equal to V
BB
. Internal 75kΩ pulldown to V
EE
.
28 3 CLK0 Noninverting Differential Clock Input 0. Internal 105kΩ pulldown to V
EE
.
Exposed
Exposed
Pad
—Internally Connected to V
EE