Datasheet

MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
44Maxim Integrated
Table 15. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
BITS NAME VALUE FUNCTION
DEFAULT
VALUE
0x07
D7 DBL
0
Single-input mode.
0
1 Double-input mode.
D6 DRS
0 High data-rate mode.
0
1 Low data-rate mode.
D5 BWS
0 24-bit mode.
0
1 32-bit mode.
D4 ES
0
Input data latched on rising edge of PCLKIN.
Power-up default determined by CONF1 and
CONF0 (Table 9). Do not change this value while
the pixel clock is running.
0, 1
1
Input data latched on falling edge of PCLKIN.
Power-up default determined by CONF1 and
CONF0 (Table 9). Do not change this value while
the pixel clock is running.
D3 — 0 Reserved. 0
D2 HVEN
0 HS/VS encoding disabled.
0
1 HS/VS encoding enabled.
D[1:0] EDC
00
1-bit parity error detection
(GMSL compatible).
00
01 6-bit CRC error detection.
10
6-bit hamming code (single-bit error correct,
double-bit error detect) and 16- word interleaving.
11 Do not use.
0x08
D7 INVVS
0 No VS or DIN0 inversion.
0
1
Invert VS when HVEN = 1.
Invert DIN0 when HVEN = 0.
Do not use if DBL = 0 in the serializer and
DBL = 1 in the deserialize
r.
D6 INVHS
0 No HS or DIN1 inversion
0
1
Invert HS when HVEN = 1.
Invert DIN1 when HVEN = 0.
Do not use if DBL = 0 in the serializer and
DBL = 1 in the deserializer.
D[5:0] — 000000 Reserved. 000000
0x09
D[7:1] I2CSRCA XXXXXXX I
2
C address translator source A. 0000000
D0 — 0 Reserved. 0
0x0A
D[7:1] I2CDSTA XXXXXXX I
2
C address translator destination A. 0000000
D0 — 0 Reserved. 0
0x0B
D[7:1] I2CSRCB XXXXXXX I
2
C address translator source B. 0000000
D0 — 0 Reserved. 0