Datasheet

MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
40Maxim Integrated
Figure 34. Human Body Model ESD Test Circuit
Figure 35. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Figure 36. ISO 10605 Contact Discharge ESD Test Circuit
Board Layout
Separate the LVCMOS logic signals and CML/coax high-
speed signals to prevent crosstalk. Use a four-layer PCB
with separate layers for power, ground, CML/coax, and
LVCMOS logic signals. Layout PCB traces close to each
other for a 100I differential characteristic impedance.
The trace dimensions depend on the type of trace used
(microstrip or stripline). Note that two 50I PCB traces
do not have 100I differential impedance when brought
close together—the impedance goes down when the
traces are brought closer. Use a 50I trace for the single-
ended output when driving coax.
Route the PCB traces for differential CML in parallel to
maintain the differential characteristic impedance. Avoid
vias. Keep PCB traces that make up a differential pair
equal length to avoid skew within the differential pair.
ESD Protection
ESD tolerance is rated for Human Body Model, IEC
61000-4-2, and ISO 10605. The ISO 10605 and IEC
61000-4-2 standards specify ESD tolerance for electronic
systems. The serial outputs are rated for ISO 10605 ESD
protection and IEC 61000-4-2 ESD protection. All pins
are tested for the Human Body Model. The Human Body
Model discharge components are C
S
= 100pF and R
D
=
1.5kI (Figure 34). The IEC 61000-4-2 discharge compo-
nents are C
S
= 150pF and R
D
= 330I (Figure 35). The
ISO 10605 discharge components are C
S
= 330pF and
R
D
= 2kI (Figure 36).
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
1MI
R
D
1.5kI
C
S
100pF
C
S
150pF
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
R
D
330I
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
R
D
2kI
C
S
330pF