Datasheet

MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
30Maxim Integrated
beyond storing the register address (Figure 28). Any
bytes received after the register address are data bytes.
The first data byte goes into the register selected by the
register address, and subsequent data bytes go into
subsequent registers (Figure 29). If multiple data bytes
are transmitted before a STOP condition, these bytes
are stored in subsequent registers because the register
addresses autoincrement.
Format for Reading
The serializer/deserializer are read using the internally
stored register address as an address pointer, the same
way the stored register address is used as an address
pointer for a write. The pointer autoincrements after each
data byte is read using the same rules as for a write. Thus,
a read is initiated by first configuring the register address
by performing a write (Figure 30). The master can now
read consecutive bytes from the device, with the first data
byte being read from the register address pointed by
the previously written register address. Once the master
sends a NACK, the device stops sending valid data.
I
2
C Communication with Remote-Side Devices
The serializer supports I
2
C communication with a periph-
eral on the remote side of the communication link using
SCL clock stretching. While multiple masters can reside
on either side of the communication link, arbitration is not
provided. The connected masters need to support SCL
clock stretching. The remote-side I
2
C bit-rate range must
be set according to the local-side I
2
C bit rate. Supported
remote-side bit rates can be found in Table 4. Set the
I2CMSTBT (register 0x0D) to set the remote I
2
C bit-rate. If
using a bit rate different than 400kbps, local- and remote-
side I
2
C setup and hold times should be adjusted by set-
ting the SLV_SH register settings on both sides.
I
2
C Address Translation
The serializer supports I
2
C address translation for up to
two device addresses. Use address translation to assign
unique device addresses to peripherals with limited
I
2
C addresses. Source addresses (address to translate
from) are stored in registers 0x09 and 0x0B. Destination
addresses (address to translate to) are stored in
registers 0x0A and 0x0C.
Figure 30. Format for I
2
C Read
Table 4. I
2
C Bit-Rate Ranges
LOCAL BIT RATE REMOTE BIT-RATE RANGE I2CMSTBT SETTING
f > 50kbps Up to 1Mbps Any
20kbps > f > 50kbps Up to 400kbps Up to 110
f < 20kbps Up to 10kbps 000
S = START BIT
P = STOP BIT
A = ACK
N = NACK
D_ = DATA BIT
S
S
1 0 0 0
ADDRESS = 0x80
0 = WRITE
0 0 0 0 A
1 = READ
REPEATED START
0 0 0 0
REGISTER ADDRESS = 0x00
0 0 0 0 A
1 0 0 0
ADDRESS = 0x81
0 0 0 1 AD7 PD6 D5 D4
REGISTER 0x00 READ DATA
D3 D2 D1 D0 N