Datasheet

MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
22Maxim Integrated
The parallel input has two input modes: single- and
double-rate input. In single-input mode, LATCH A stores
data from DIN_ every PCLKIN cycle (Figure 13). Parallel
data from LATCH A is then sent to the scrambler for
serialization (Figure 14). The device accepts pixel clocks
from 6.25MHz to 50MHz.
In double-input mode, LATCH B stores two input words
(Figure 15). Data from LATCH B is sent to the scrambler
as a combined word. The MAX9272 deserializer outputs
the combined word (single-output mode) or two half-sized
words (double-output mode). The serializer/deserializer
use pixel clock rates from 33.3MHz to 100MHz for 11-bit,
double-input mode and 25MHz to 75MHz for 15-bit,
double-input mode. See Figure 16 for timing details.
Figure 13. Single-Input Waveform (Latch on Rising Edge of PCLKIN Selected)
Figure 14. Single-Input Function Block Figure 15. Double-Input Function Block
FIRST WORD
FIRST WORD
PCLKIN
DIN0–DIN21
LATCH A
SECOND WORD
SECOND WORD
THIRD WORD
THIRD WORD
FOURTH WORD
FOURTH WORD
DIN0–DIN21
INPUT
LATCH A
PCLKIN
MAX9273
PCLKIN
DIN0–DIN14
OR
DIN0–DIN10
INPUT
LATCH B
INPUT
LATCH B
÷ 2
MAX9273