Datasheet

49Maxim Integrated
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Table 17. MAX9260 Register Table (continued)
X = Don’t care.
Typical Application Circuit
REGISTER
ADDRESS
BITS NAME VALUE FUNCTION
DEFAULT
VALUE
0x07 D[7:0] — 01010100 Reserved 01010100
0x08 D[7:0] — 00110000 Reserved 00110000
0x09 D[7:0] — 11001000 Reserved 11001000
0x0A D[7:0] — 00010010 Reserved 00010010
0x0B D[7:0] — 00100000 Reserved 00100000
0x0C D[7:0] ERRTHR XXXXXXXX
Error threshold for decoding errors. ERR =
low when DECERR > ERRTHR.
00000000
0x0D D[7:0] DECERR XXXXXXXX
Decoding error counter. This counter remains
zero while the device is in PRBS test mode.
00000000
(read only)
0x0E D[7:0] PRBSERR XXXXXXXX PRBS error counter
00000000
(read only)
0x12
D7 MCLKSRC
0 MCLK derived from PCLKOUT (see Table 3)
0
1 MCLK derived from internal oscillator
D[6:0] MCLKDIV
0000000 MCLK disabled
0000000
XXXXXXX MCLK divider
0x1E D[7:0] ID 00000010
Device identifier
(MAX9260 = 0x02)
00000010
(read only)
0x1F
D[7:4] — 0000 Reserved
0000
(read only)
D[3:0] REVISION XXXX Device revision (read only)
PCLK
RGB
HSYNC
VIDEO
ECU
UART
VSYNC
TX
RX
INT
IMS
AUDIO
WS
SCK
SD
PCLKIN
DIN(0:27)
DIN28
CDS
AUTOS
LMN0
LMN1
OUT-
OUT+
RX/SDA
TX/SCL
INT
WS
MS
SD
SCK
SCL
SDA
PCLKOUT
DOUT(0:27)
CDS
INT
RX/SDA
TX/SCL
LOCK
IN+
1.8V
IN-
WS
SD
SCK
DOUT28/MCLK
4.99kI4.99kI
45.3kI45.3kI
49.9kI49.9kI
WS
SD
SCK
MCLK
PCLK
HSYNC
RGB
VSYNC
TO PERIPHERALS
DISPLAY
MAX9850
MAX9260
MAX9259
LFLT LFLT