Datasheet
28 Maxim Integrated
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Parallel Data-Rate Selection
The MAX9259/MAX9260 use the DRS inputs to set the
parallel data rate. Set DRS high to use a low-speed par-
allel data rate in the range of 6.25MHz to 12.5MHz (32-bit
mode) or 8.33MHz to 16.66MHz (24-bit mode). Set DRS
low for normal operation with parallel data rates higher
than 12.5MHz (32-bit mode) or 16.66MHz (24-bit mode).
Audio Channel
The I
2
S audio channel supports audio sampling rates
from 8kHz to 192kHz and audio word lengths from 4 bits
to 32 bits. The audio bit clock (SCK) does not need to be
synchronized with PCLKIN. The MAX9259 automatically
encodes audio data into a single bit stream synchronous
with PCLKIN. The MAX9260 decodes the audio stream
and stores audio words in a FIFO. Audio rate detection
uses an internal oscillator to continuously determine the
audio data rate and output the audio in I
2
S format. The
audio channel is enabled by default. When the audio
channel is disabled, the SD pins on both sides are
treated as a regular parallel data pin.
PCLK_ frequencies can limit the maximum supported
audio sampling rate. Table 2 lists the maximum audio
sampling rate for various PCLK_ frequencies. Spread-
spectrum settings do not affect the I
2
S data rate or WS
clock frequency.
Additional MCLK Output
for Audio Applications
Some audio DACs such as the MAX9850 do not require
a synchronous main clock (MCLK), while other DACs
require MCLK to be a specific multiple of WS. If an audio
DAC chip needs the MCLK to be a multiple of WS, syn-
chronize the I
2
S audio data with PCLK_ of the GMSL,
which is typical for most applications. Select the PCLK_
to be the multiple of WS, or use a clock synthesis chip,
such as the MAX9491, to regenerate the required MCLK
from PCLK_ or SCK.
For audio applications that cannot directly use the
PCLKOUT output, the MAX9260 provides a divided
MCLK output on DOUT28 at the expense of one less
parallel line in 32-bit mode (24-bit mode is not affected).
By default, DOUT28 operates as a parallel data output
and MCLK is turned off. Set MCLKDIV (MAX9260 regis-
ter 0x12, D[6:0]) to a non-zero value to enable the MCLK
output. Set MCLKDIV to 0x00 to disable MCLK and set
DOUT28 as a parallel data output.
The output MCLK frequency is:
SRC
MCLK
f
f
MCLKDIV
=
where f
SRC
is the MCLK source frequency (Table 3) and
MCLKDIV is the divider ratio from 1 to 127.
Table 2. Maximum Audio Sampling Rates for Various PCLK_ Frequencies
WORD LENGTH
(Bits)
PCLK_ FREQUENCY
(DRS = LOW)
(MHz)
PCLK_ FREQUENCY
(DRS = HIGH)
(MHz)
12.5 15 16.6 > 20 6.25 7.5 8.33 > 10
8
> 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192
16
> 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192
18
185.5 > 192 > 192 > 192 185.5 > 192 > 192 > 192
20
174.6 > 192 > 192 > 192 174.6 > 192 > 192 > 192
24
152.2 182.7 > 192 > 192 152.2 182.7 > 192 > 192
32
123.7 148.4 164.3 > 192 123.7 148.4 164.3 > 192