Datasheet

27Maxim Integrated
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Parallel Inputs and Outputs
The parallel bus uses two selectable bus widths, 24
bits and 32 bits. BWS selects the bus width according
to Table 1. In 24-bit mode, DIN21–DIN28 are not used
and are internally pulled down. For both modes, SD,
SCK, and WS pins are dedicated for I
2
S audio data. The
assignments of the first 21 or 29 signals are interchange-
able and appear in the same order at both sides of the
serial link. In image-sensing applications, disabling the
I
2
S audio channel (through the MAX9259 and MAX9260
internal registers) allows the MAX9259 to serialize three
10-bit camera data streams through DIN[0:28] plus SD
inputs. The parallel bus accepts data clock rates from
8.33MHz to 104MHz for the 24-bit mode and 6.25MHz to
78MHz for the 32-bit mode.
Serial Link Signaling and Data Format
The MAX9259 high-speed data serial output uses
CML signaling with programmable preemphasis and
AC-coupling. The MAX9260 high-speed receiver uses
AC-coupling and programmable channel equalization.
Together, the GMSL operates at up to 3.125Gbps over
STP cable lengths up to 15m.
The serializer scrambles and encodes the parallel input
bits, and sends the 8B/10B coded signal through the
serial link. The deserializer recovers the embedded
serial clock and then samples, decodes, and descram-
bles the data onto the parallel output bus. Figures 22
and 23 show the serial-data packet format prior to
scrambling and 8B/10B coding. For the 24-bit or 32-bit
mode, the first 21 or 29 serial bits come from DIN[20:0]
or DIN[28:0], respectively. The audio channel bit (ACB)
contains an encoded audio signal derived from the three
I
2
S inputs (SD, SCK, and WS). The forward control chan-
nel (FCC) bit carries the forward control data. The last bit
(PCB) is the parity bit of the previous 23 or 31 bits.
Reverse Control Channel
The MAX9259/MAX9260 use the reverse control channel
to send I
2
C/UART and interrupt signals in the opposite
direction of the video stream from the deserializer to
the serializer. The reverse control channel and forward
video data coexist on the same twisted pair forming a
bidirectional link. The reverse control channel operates
independently from the forward control channel. The
reverse control channel is available 500Fs after power-
up. The MAX9259 temporarily disables the reverse con-
trol channel for 350Fs after starting/stopping the forward
serial link.
Table 1. Bus-Width Selection Using BWS
Figure 22. 24-Bit Mode Serial Link Data Format Figure 23. 32-Bit Mode Serial Link Data Format
24 BITS
DIN0 DIN1
18-BIT
RGB
DATA
HSYNC,
VSYNC,
DE
AUDIO
CHANNEL BIT
FORWARD
CONTROL-
CHANNEL BIT
PACKET
PARITY
CHECK BIT
NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE
INTERCHANGEABLE ACCORDINGLY ON BOTH SIDES OF THE LINK.
DIN17 DIN18 DIN19 DIN20 ACB FCC PCB
24-BIT
RGB DATA
HSYNC,
VSYNC,
DE
ADDITIONAL
VIDEO
DATA/
CONTROL
BITS
AUDIO
CHANNEL
BIT
FORWARD
CONTROL-
CHANNEL
BIT
PACKET
PARITY
CHECK BIT
NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE
INTERCHANGEABLE ACCORDINGLY ON BOTH SIDES OF THE LINK.
32 BITS
DIN0 DIN1 DIN23 DIN24 DIN25 DIN26 DIN27 DIN28 ACB FCC PCB
BWS INPUT STATE BUS WIDTH PARALLEL BUS SIGNALS USED
Low 24 DIN[0:20]/DOUT[0:20], WS, SCK, SD
High 32 DIN[0:28]/DOUT[0:28], WS, SCK, SD