Datasheet

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MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
MAX9257A AC ELECTRICAL CHARACTERISTICS
(V
CC_
= +3.0V to +3.6V, V
CCIO
= +1.71V to +3.6V, R
L
= 50I Q1%, T
A
= -40NC to +105NC, unless otherwise noted. Typical values are
at V
CC_
= +3.3V, T
A
= +25NC.) (Notes 5, 9)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PCLK�IN TIMING REQUIREMENTS
Clock Period t
T
14.28 200.00 ns
Clock Frequency f
CLK
1/t
T
5 70 MHz
Clock Duty Cycle DC t
HIGH
/t
T
or t
LOW
/t
T
35 50 65 %
Clock Transition Time t
R
, t
F
(Figure 7) 4 ns
SWITCHING CHARACTERISTICS
LVDS Output Rise Time t
R
20% to 80% (Figure 4) 315 370 ps
LVDS Output Fall Time t
F
20% to 80% (Figure 4) 315 370 ps
Control Transceiver Transition
Time
t
R1A
, t
F1A
20% to 80% (Figure 16)
642 970 1390
pst
R2
, t
F2
810 1140 1420
t
R1B
, t
F1B
290 386 490
Input Setup Time t
S
(Figure 5) 0 ns
Input Hold Time t
H
(Figure 5) 3 ns
Parallel-to-Serial Delay
t
PSD1
Spread off (Figure 6)
(4.55 x t
T)
+ 11
ns
t
PSD2
Q4% spread
(36.55 x t
T)
+ 11
PLL Lock Time t
LOCK
Combined FPLL and SPLL; PCLK_IN stable
32,768
x t
T
ns
Random Jitter t
RJ
420MHz LVDS output, spread off,
FPLL = bypassed
12
ps
(RMS)
Deterministic Jitter t
DJ
2
18
- 1 PRBS, SRATE = 840Mbps, 18 bits,
no spread
142 ps (P-P)
SCL/TX, SDA/RX
Rise Time t
RS
0.3 x V
CCIO
to 0.7 x
V
CCIO
, C
L
= 30pF
R
PULLUP
= 10kI
400
ns
R
PULLUP
= 1.6kI
60
Fall Time t
FS
0.7 x V
CCIO
to 0.3 x V
CCIO,
C
L
= 30pF 40 ns
Pulse Width of Spike Suppressed
in SDA
t
SPK
95kbps to 400kbps 100
ns
400kbps to 1000kbps 50
1000kbps to 4250kbps 10
DC to 10Mbps (bypass mode) 10
Data Setup Time t
SETUP
400kbps 100
ns
4.25Mbps, C
L
= 10pF 60
Data Hold Time t
HOLD
400kbps 100
ns
4.25Mbps, C
L
= 10pF 0