Datasheet

Evaluates: MAX9257A/MAX9258A

By default, the MAX9258A, MAX9257A, and the emulat-

ed camera use the UART interface (JU26 and JU27

shunts are set across pins 1-2). Press the Turn On D4,

Turn Off D4, Fast Blink D4, and Slow Blink D4 but-

tons to demonstrate several simple communication

trans-actions between the ECU and the camera.

A user can change the UART speed, enable/disable

the video clocks (PCLK_IN, HSYNC_IN, and

VSYNC_IN), select different video clock speeds, and

switch the camera to the I

C interface. See the

Configuration Examples

section for details.

The EV kit can generate PCLK_IN, HSYNC_IN, and

VSYNC_IN signals with the following relationships:

HSYNC_IN = PCLK_IN/1000 and VSYNC_IN =

PCLK_IN/500000. By default they are not enabled, so

that an external pattern generator or piece of video

equipment can be connected to J6. If the Enable

PCLK_IN/HSYNC_IN/VSYNC_IN button is pressed, the

signals are enabled and the status of these three sig-

nals are displayed in the Onboard PCLK_IN,

HSYNC_IN, VSYNC_IN Status group box.

By default, PCLK_IN is 30MHz, HSYNC_IN is 30kHz,

and VSYNC_IN is 60Hz. The duty cycles of all the sig-

nals are fixed at 50%.

Configuration Examples

This section describes how to configure the SerDes to

work in UART Never Come Back Operation, UART

With Finite CTO Operation, and I

C Mode. Use an

oscilloscope to monitor the activity on the MAX9258A

TX, RX, and CCEN pins.

MAX9257A/MAX9258A Evaluation Kit

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Figure 4. MAX9257A/MAX9258A Evaluation Kit Software—Deserializer MAX9258A Tab