Datasheet

Description of IP Cores
The EV kit implements two digital cores on the FPGA
devices to generate high-speed UART signals and to
emulate a high-speed I
2
C slave device.
D16750 Core
(Provided by Digital Core Design)
The D16750 is an IP core of a universal asynchronous
receiver-transmitter (UART), functionally identical to the
TL16C750. Contact Digital Core Design for questions
relating to the D16750 IP core. See the Component
Suppliers section for contact information or email Digital
Core Design at [e-mail] for more information.
DI2CS Core
(Provided by Digital Core Design)
The DI2CS is an IP core that provides an interface
between a microprocessor and an I
2
C bus. It can work
as a slave receiver or transmitter depending on the
working mode determined by a microprocessor/micro-
controller. The DI2CS core supports all of the transmis-
sion modes required by the I
2
C specification (standard,
fast, and high speed). Contact Digital Core Design for
any questions relating to the DI2CS IP core. See the
Component Suppliers section for contact information or
email Digital Core Design at [e-mail] for more infor-
mation.
Evaluates: MAX9257A/MAX9258A
MAX9257A/MAX9258A Evaluation Kit
______________________________________________________________________________________ 11
JUMPER SETTING DESCRIPTION
1-2* MAX9258A PD pin is pulled up to V
CC
by a 1kΩ resistor
JU1
Open MAX9258A PD pin is internally pulled down to ground
JU2 Open* MAX9258A LVDS line probing connector
JU3 Open* MAX9258A LVDS line probing connector
1-2* MAX9258A ERROR pin is pulled up to V
CCOUT
by a 1kΩ resistor
JU4
Open MAX9258A ERROR pin is open-drain output
1-2* MAX9258A LOCK pin is pulled up to V
CCOUT
by a 1kΩ resistor
JU5
Open MAX9258A LOCK pin is open-drain output
1-2* MAX9258A V
CC
connected to on-board LDO 3.3V output
JU6
Open MAX9258A V
CC
connected to an external power supply
1-2* MAX9258A V
CCOUT
connected to on-board LDO 3.3V output
JU7
Open MAX9258A V
CCOUT
connected to an external power supply
1-2* MAX9258A V
CCPLL
connected to on-board LDO 3.3V output
JU8
Open MAX9258A V
CCPLL
connected to an external power supply
1-2* MAX9258A V
CCSPLL
connected to on-board LDO 3.3V output
JU9
Open MAX9258A V
CCSPLL
connected to an external power supply
1-2* MAX9258A V
CCLVDS
connected to on-board LDO 3.3V output
JU10
Open MAX9258A V
CCLVDS
connected to an external power supply
1-2 MAX9258A is powered by on-board LDO U5, whose V
DD
input range is 3.5V to 12V
JU11
2-3* MAX9258A is powered by on-board LDO U4, whose input is 5V
1-2 MAX9258A LVDS cable line-1 connected to VDD
JU14
2-3* MAX9258A LVDS cable line-1 connected to ground
1-2* MAX9258A RX pin is connected to the on-board emulated ECU RX line
JU15
Open
MAX9258A RX pin is disconnected from the on-board emulated ECU RX line (an external ECU RX
line can connect to J1-37)
1-2* MAX9258A TX pin is connected to the on-board emulated ECU TX line
JU16
Open
MAX9258A TX pin is disconnected from the on-board emulated ECU TX line (an external ECU TX
line can connect to J1-35)
Table 1. EV Kit Jumper Settings