Datasheet
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MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
LVDS Termination
Terminate the LVDS link at both ends with the charac-
teristic impedance of the transmission line (typically
100O differential). The LVDS inputs and outputs are high
impedance to GND and differentially.
Spread-Spectrum Selection
The devices each have spread-spectrum options. Both
should not be turned on at the same time. When the
MAX9257A is programmed for spread spectrum, the
MAX9258A tracks and passes the spread to its clock and
data outputs. The MAX9257A/MAX9258A are both center
spread (Figure 21). The control channel does not use
spread spectrum, but has slower transition times.
MAX9258A Spread Spectrum
The MAX9258A features a programmable spread-spec trum
clock and data outputs for reduced EMI. The sin gle-ended
data outputs are programmable for no spread, Q2%, or
Q4% (see the Typical Operating Characteristics) around the
recovered pixel clock fre quency. The output spread is pro-
grammed in register REG1[7:6]. Table 17 shows the spread
options, and Table 18 shows the various modulation rates.
MAX9257A Spread Spectrum
The MAX9257A features programmable spread spec-
trum for the LVDS outputs. Table 19 shows various
spread options, and Table 20 shows the various modu-
lation rates. Only one device (the MAX9257A or the
MAX9258A) should be programmed for spread spectrum
at a time. If the MAX9257A is programmed for spread,
the MAX9258A tracks and passes the spread to the data
and clock out puts. The PRATE range of 00 and 01 (5MHz
≤ PCLK ≤ 20MHz) supports all the spread options. The
PRATE range of 10 and 11 (20MHz ≤ PCLK ≤ 70MHz)
requires that the spread be 2% or less.
Pixel Clock Jitter Filter
The MAX9257A has a PLL to filter high-frequency pixel
clock jitter on PCLK_IN. The FPLL can be bypassed by
writing 1 to REG4[2]. The FPLL improves the MAX9258A’s
data recovery by filtering out the high-fre quency compo-
nents from the pixel clock that the MAX9258A cannot
track. The 3dB bandwidth of the FPLL is 100kHz (typ).
Figure 21. Simplified Modulation Profile for the MAX9257A/
MAX9258A
Table 16. Parallel-Word Width
Table 17. MAX9258A Spread
Table 18. MAX9258A Modulation Rate
Table 19. MAX9257A LVDS Output Spread
PARALLEL-WORD WIDTH PWIDTH (REG0[2:0])
10 000
12 001
14 010
16 011
18 1XX
PRATE (REG1[7:6]) SPREAD (%)
00 Off
01
Q2
10 Off
11
Q4
PRATE
(REG1[7:6])
MODULATION RATE f
SSM
RANGE (kHz)
00 PCLK/312 16 to 32
01 PCLK/520 19.2 to 38.5
10 PCLK/1040 19.2 to 38.5
11 PCLK/1248 32 to 56
REG1[7:5] SPREAD (%)
000 Off
001
Q1.5
010
Q1.75
011
Q2
100 Off
101
Q3
110
Q3.5
111
Q4
FREQUENCY
TIME
f
SPREAD
(MAX)
f
PCLK_IN
f
SPREAD
(MIN)
1/f
SSM