Datasheet
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MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
The video data are coded using two overhead bits (EN0
and EN1) resulting in a serial-word length of N+2 bits.
The devices feature programmable parity encoding that
adds two parity bits to the serial word. Bit 0 (EN0) is the
LSB that is serialized first with out parity enabled. The par-
ity bits are serialized first when parity is enabled.
The ECU programs the MAX9258A, MAX9257A, and
peripheral devices at startup and during the control
channel phase. In a digital video system, the control
channel phase occurs during the vertical blanking time
and synchronizes to the VSYNC signal. The programma-
ble active edge of VSYNC initiates the control channel
phase. Nonactive edge of VSYNC can transition at any
time after 8 x t
T
if MAX9257A spread is not enabled and
0.5/f
SSM
when enabled. At the end of video phase, the
MAX9258A drives CCEN high to indicate to the ECU
that the control channel is open. Programmable timers
and ECU signal activity determine how long the control
channel stays open. The timers are reset by ECU signal
activity. ECU programming must not exceed the vertical
blanking time to avoid loss of video data.
After the control channel phase closes, the MAX9257A
sends a 546 or 1090 word pattern as handshaking (HSK)
to synchronize the MAX9258A’s internal clock recovery
circuit to the MAX9257A’s transmitted data. Following
the handshaking, the control channel is closed and the
video phase begins. The serial LVDS data is recovered
and parallel data is valid on the pro grammed edge of the
recovered pixel clock.
Table 1 and 2 show the default power-up values for the
MAX9257A/MAX9258A registers. Tables 3 and 4 show
the input and output supply references.
Table 1. MAX9257A Power-Up Default Register Map (see the MAX9257A Register Table)
REGISTER NAME
REGISTER
ADDRESS (hex)
POWER-UP VALUE
(hex)
POWER-UP DEFAULT SETTINGS
REG0 0x00 0xB5
PRATE = 10, 20MHz to 40MHz
SRATE = 11, 400Mbps to 840Mbps
PAREN = 0, parity disabled
PWIDTH = 101, parallel data width = 18
REG1 0x01 0x1F
SPREAD = 000, spread = off
Reserved = 11111
REG2 0x02 0xA0
STODIV = 1010, STO clock is pixel clock divided by 1024
STOCNT = 0000, STO counter counts to 1
REG3 0x03 0xA0
ETODIV = 1010, ETO clock is pixel clock divided by 1024
ETOCNT = 0000, ETO counter counts to 1
REG4 0x04
1) REM = 0, 0x28
2) REM = 1, 0x30
VEDGE = 0, VSYNC active edge is falling
Reserved = 0
CKEDGE = 1, pixel clock active edge is rising
PD: 1) If REM = 0, PD = 0
2) If REM = 1, PD = 1
SEREN: 1) If REM = 0, SEREN = 1
2) If REM = 1, SEREN = 0
BYPFPLL = 0, filter PLL is active
Reserved = 0
PRBSEN = 0, PRBS test disabled