Datasheet

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MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
Figure 6. MAX9257A Parallel-to-Serial Delay
Figure 7. MAX9257A Parallel Input Clock Requirements
Figure 8. MAX9258A Worst-Case Pattern Output Figure 9. MAX9258A Output Rise and Fall Times
t
PSD1
FIRST BIT LAST BIT
N
N+3
EXPANDED TIME SCALE
N+4
N
N+1
N+2
N-1
DIN, HSYNC_IN,
VSYNC_IN
PCLK_IN
SDO
V
ILMAX
t
HIGH
t
LOW
t
T
t
R
t
F
V
IHMIN
PCLK_IN
PCLK_OUT
DOUT
NOTE: PCLK_OUT PROGRAMMED FOR RISING LATCH EDGE.
0.9 x V
CCOUT
0.1 x V
CCOUT
t
F
t
R
C
L
SINGLE-ENDED OUTPUT LOAD
MAX9258A