Datasheet

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MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
MAX9258A Pin Description (continued)
PIN NAME FUNCTION
16 TX LVCMOS/LVTTL Control Channel UART Input. TX is internally pulled up to V
CCOUT
.
17 LOCK
Open-Drain Lock Output. LOCK asserts high to indicate PLLs are locked with correct serial-word
boundary alignment. LOCK asserts low to indicate PLLs are not locked or incorrect serial-word
boundary alignment was detected. Pull up to V
CCOUT
with a 1kI resistor.
18 PCLK_OUT LVCMOS/LVTTL Recovered Clock Output
19 VSYNC_OUT LVCMOS/LVTTL Vertical SYNC Output
20 HSYNC_OUT LVCMOS/LVTTL Horizontal SYNC Output
21, 28–35,
40–46
DOUT[15:0] LVCMOS/LVTTL Data Outputs
22, 39 V
CCOUT
Output Supply Voltage. V
CCOUT
is the supply for all output buffers. Bypass V
CCOUT
to GNDOUT
with 0.1FF and 0.001FF capacitors in parallel as close as possible to the device with the smallest
value capacitor closest to V
CCOUT
.
23, 38, 48 GNDOUT Output Supply Ground
26 V
CCSPLL
Spread-Spectrum PLL Supply Voltage. Bypass V
CCSPLL
to GNDSPLL with 0.1FF and 0.001FF
capacitors in parallel as close as possible to the device with the smallest value capacitor closest to
V
CCSPLL
.
27 GNDSPLL SPLL Ground
47
CCEN
LVCMOS/LVTTL Control Channel Enabled Output. CCEN asserts high to indicate that control chan-
nel is enabled.