Datasheet

27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
8 Maxim Integrated
MAX9248/MAX9250
Functional Diagram
IN+
IN-
REFCLK
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
1
0
RGB_OUT
LOCK
PWRDWN
SS
PCLK_OUT
DE_OUT
CNTL_OUT
SSPLL
FIFO
RNG[0:1]
R/F
RNG[0:1]
IN+
IN-
REFCLK
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
1
0
OUTEN
RGB_OUT
LOCK
PWRDWN
REF_IN
PCLK_OUT
DE_OUT
CNTL_OUT
R/F
MAX9250
MAX9248
Pin Description (continued)
PIN
MAX9248
MAX9250
NAME FUNCTION
27 27 LOCK LVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low.
28 28
PCLK_OUT
LV TTL/LV C M OS P ar al lel Cl ock Outp ut. Latches d ata i nto the next chi p on the ed g e selected b y R/F.
29–36,
39–48
29–36,
39–48
RGB_OUT0–
RBG_OUT7,
RGB_OUT8–
RGB_OUT17
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Outputs. RGB_OUT[17:0] are
latched into the next chip on the edge of PCLK_OUT selected by R/F when DE_OUT is high,
and are held at the last state when DE_OUT is low.
— 14 OUTEN
LVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs. Driving
low places the single-ended outputs in high impedance except LOCK. Internally pulled
down to GND.