Datasheet

27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
Maxim Integrated 5
MAX9248/MAX9250
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
TH
and V
TL
.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T
A
= +25°C.
Note 3: Parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 4: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ V
CC
- 0.3V. PWRDWN is ≤ 0.3V, REFCLK is static.
Note 5: C
L
includes probe and test jig capacitance.
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC_
= +3.0V to +3.6V, C
L
= 8pF, PWRDWN = high, differential input voltage ⏐V
ID
⏐ = 0.1V to 1.2V, input common-mode voltage
V
CM
= ⏐V
ID
/ 2⏐ to V
CC
- ⏐V
ID
/ 2⏐, T
A
= -40°C to +105°C, unless otherwise noted. Typical values are at V
CC_
= +3.3V, ⏐V
ID
⏐ = 0.2V,
V
CM
= 1.2V, T
A
= +25°C.) (Notes 3, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Maximum output
frequency
f
REFCLK
+ 3.6%
f
REFCLK
+ 4.0%
f
REFCLK
+ 4.4%
SS = high,
Figure 11
Minimum output
frequency
f
REFCLK
- 4.4%
f
REFCLK
- 4.0%
f
REFCLK
- 3.6%
Maximum output
frequency
f
REFCLK
+ 1.8%
f
REFCLK
+ 2.0%
f
REFCLK
+ 2.2%
Spread-Spectrum Output
Frequency (MAX9248)
f
PCLK_OUT
SS = low,
Figure 11
Minimum output
frequency
f
REFCLK
- 2.2%
f
REFCLK
- 2.0%
f
REFCLK
- 1.8%
MHz
Spread-Spectrum Modulation
Frequency
f
SSM
Figure 11
f
REFCLK
/
1024
kHz
Power-Down Delay t
PDD
Figures 7, 8 100 ns
SS Change Delay t
SSPLL
MAX9248, Figure 17
32,800
x t
T
ns
Output Enable Time t
OE
MAX9250, Figure 8 10 30 ns
Output Disable Time t
OZ
MAX9250, Figure 9 10 30 ns