Datasheet

27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
14 Maxim Integrated
MAX9248/MAX9250
PAR-TO-SER
TIMING AND
CONTROL
DC BALANCE/
ENCODE
INPUT LATCH
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
1
0
130Ω
V
CC
130Ω
IN+
IN-
OUT
82Ω 82Ω
CMF
PRE
REFCLK
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
1
0
RGB_OUT
LOCK
PWRDWN
SS
PCLK_OUT
DE_OUT
CNTL_OUT
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
PLL
*
*
*CAPACITORS CAN BE AT EITHER END.
SSPLL
FIFO
RNG[0:1]
R/F
MAX9248
MAX9247
Figure 14. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Two Capacitors per Link
PAR-TO-SER
TIMING AND
CONTROL
DC BALANCE/
ENCODE
INPUT LATCH
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
1
0
130Ω
V
CC
130Ω
IN+
IN-
OUT
82Ω 82Ω
CMF
PRE
REFCLK
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
1
0
RGB_OUT
LOCK
PWRDWN
SS
PCLK_OUT
DE_OUT
CNTL_OUT
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
PLL
SSPLL
FIFO
RNG[0:1]
R/F
MAX9248
MAX9247
Figure 15. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Four Capacitors per Link