Datasheet

27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
Maxim Integrated 13
MAX9248/MAX9250
PAR-TO-SER
TIMING AND
CONTROL
PLL
DC BALANCE/
ENCODE
INPUT LATCH
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
1
0
130Ω
V
CC
130Ω
IN
OUT
82Ω 82Ω
RNG1
RNG0
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
1
0
OUTEN
RGB_OUT
LOCK
PWRDWN
REF_IN
PCLK_OUT
DE_OUT
CNTL_OUT
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
*CAPACITORS CAN BE AT EITHER END.
*
*
R/F
CMF
PRE
MAX9250
MAX9247
Figure 12. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Two Capacitors per Link
PAR-TO-SER
TIMING AND
CONTROL
PLL
DC BALANCE/
ENCODE
INPUT LATCH
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
1
0
130Ω
V
CC
130Ω
IN
OUT
82Ω 82Ω
RNG1
RNG0
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
1
0
OUTEN
RGB_OUT
LOCK
PWRDWN
REF_IN
PCLK_OUT
DE_OUT
CNTL_OUT
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
CMF
PRE
R/F
MAX9250
MAX9247
Figure 13. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Four Capacitors per Link