Datasheet

27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
10 Maxim Integrated
MAX9248/MAX9250
PWRDWN
REFCLK
PCLK_OUT
RGB_OUT
CNTL_OUT
DE_OUT
LOCK
t
PLLREF
TRANSITION
WORD
FOUND
RECOVERED CLOCK
CLOCK STRETCH
VALID DATA
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
NOTE: R/F = HIGH
t
PDD
0.8V
2.0V
Figure 7. PLL Lock to REFCLK and Power-Down Delay for MAX9250
PWRDWN
REFCLK
PCLK_OUT
RGB_OUT
CNTL_OUT
DE_OUT
LOCK
t
PLLREF
TRANSITION
WORD
FOUND
OUTPUT CLOCK SPREAD
CLOCK STRETCH
VALID DATA
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
NOTE: R/F = HIGH
t
PDD
0.8V
2.0V
288 CLOCK CYCLES
OUTPUT DATA SPREAD
Figure 8. PLL Lock to REFCLK and Power-Down Delay for MAX9248