Datasheet

27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
Maxim Integrated 9
MAX9248/MAX9250
PCLK_OUT
PCLK_OUT SHOWN FOR R/F = HIGH (RISING LATCH EDGE)
t
DVB
t
DVA
2.0V
2.0V2.0V
0.8V
0.8V
0.8V
DE_OUT
LOCK
RGB_OUT[17:0]
CNTL_OUT[8:0]
Figure 5. Synchronous Output Timing
IN+, IN-
PCLK_OUT
CNTL_OUT
RGB_OUT
20 SERIAL BITS
SERIAL-WORD N SERIAL-WORD N + 1
PARALLEL-WORD N - 1 PARALLEL-WORD N
t
DELAY
PCLK_OUT SHOWN FOR R/F = HIGH
Figure 6. Deserializer Delay
PCLK_OUT
t
LOW
t
HIGH
2.0V
0.8V
Figure 4. High and Low Times
DE_OUT
LOCK
PCLK_OUT
RGB_OUT[17:0]
CNTL_OUT[8:0]
0.9 x V
CCO
0.1 x V
CCO
t
F
t
R
Figure 3. Output Rise and Fall Times
LVDS
RECEIVER
1.2V
IN+
R
IB
R
IB
IN-
Figure 1. LVDS Input Bias
PCLK_OUT
ODD
RGB_OUT
CNTL_OUT
EVEN
RGB_OUT
CNTL_OUT
RISING LATCH EDGE SHOWN (R/F = HIGH).
Figure 2. Worst-Case Output Pattern