Datasheet
MAX9247/MAX9248 Evaluation Kit
Evaluates: MAX9247/MAX9248
6 ______________________________________________________________________________________
pattern, connect a logic analyzer or data-acquisition sys-
tem to H1 and H2. See Table 4 for the output bit locations
on the H1 and H2 headers.
Data-Enable Output (DE_OUT)
The MAX9248 DE_OUT pin is accessible through header
H2-21. A high output indicates that RGB_OUT[17:0] are
active and a low output indicates that CNTL_OUT[8:0]
are active.
Rising and Falling Input Latch Edge (R/F)
The MAX9248 has a selectable rising or falling output
latch edge through logic setting on the R/F pin. Drive
the R/F pin low by placing a shunt in the 1-2 position of
jumper JU1 (see Table 1). Drive the R/F pin high by plac-
ing a shunt in the 1-4 position of JU1.
Frequency Range Setting (RNG1 and RNG0)
The parallel clock frequency range for the MAX9247 can
be configured through jumpers JU14 and JU15. Place a
shunt on JU14 and JU15 to drive RNG1 and RNG0 high,
or leave JU14 and JU15 unconnected to drive RNG1 and
RNG0 low. Refer to the MAX9247 IC data sheet for actual
frequency settings.
The operating frequency range for the MAX9248 can
be configured through jumpers JU2 and JU3. Place a
shunt in the 1-4 position of JU2 and JU3 to drive RNG1
and RNG0 high, or place a shunt in the 1-2 position of
JU2 and JU3 to drive RNG1 and RNG0 low. Refer to the
MAX9248 IC data sheet for actual frequency settings.
Power-Down (PWRDWN)
The power-down mode in the MAX9247 and MAX9248
puts the outputs in high impedance, stops the PLL, and
reduces supply current to 50FA or less.
The MAX9247 PWRDWN pin is accessible through
header H6-15. Drive the pin high for normal operation
of the MAX9247 or drive the pin low to power down the
MAX9247.
The MAX9248 PWRDWN pin is accessible through
jumper JU4 (see Table 1). Drive the pin high by placing
a shunt in the 1-4 position of JU4 for normal operation.
Drive the pin low by placing a shunt in the 1-2 position of
JU4 to power down the MAX9248.
Spread-Spectrum Frequency (SS)
The MAX9248 can set the frequency spread to ±4% or
±2% by moving the shunt of jumper JU5 to the appropri-
ate position (see Table 1).
Pseudo-Random Bit Sequence (PRBS) Mode
The MAX9247/MAX9248 EV kit offers the user an internal
test mode to quickly check full functionality and verify
the quality of the SerDes link. This mode is called the
pseudo-random bit sequence, or PRBS mode.
The MAX9247 features an on-chip PRBS generator that
can be utilized to generate a pseudo-random bit stream
to evaluate the quality and performance by comparing
the output of the serializer (prior to the link/cable) with the
input of the deserializer (after the link/cable).
Table 4. Video and Control Data Outputs
OUTPUT
SIGNALS
DESIGNATION DESCRIPTION
CNTL_OUT0 H2-3 Output control bit 0
CNTL_OUT1 H2-5 Output control bit 1
CNTL_OUT2 H2-7 Output control bit 2
CNTL_OUT3 H2-9 Output control bit 3
CNTL_OUT4 H2-11 Output control bit 4
CNTL_OUT5 H2-13 Output control bit 5
CNTL_OUT6 H2-15 Output control bit 6
CNTL_OUT7 H2-17 Output control bit 7
CNTL_OUT8 H2-19 Output control bit 8
RGB_OUT0 H2-27 Output video bit 0
RGB_OUT1 H2-29 Output video bit 1
RGB_OUT2 H2-31 Output video bit 2
RGB_OUT3 H1-3 Output video bit 3
RGB_OUT4 H1-5 Output video bit 4
RGB_OUT5 H1-7 Output video bit 5
RGB_OUT6 H1-9 Output video bit 6
RGB_OUT7 H1-11 Output video bit 7
RGB_OUT8 H1-13 Output video bit 8
RGB_OUT9 H1-15 Output video bit 9
RGB_OUT10 H1-17 Output video bit 10
RGB_OUT11 H1-19 Output video bit 11
RGB_OUT12 H1-21 Output video bit 12
RGB_OUT13 H1-23 Output video bit 13
RGB_OUT14 H1-25 Output video bit 14
RGB_OUT15 H1-27 Output video bit 15
RGB_OUT16 H1-29 Output video bit 16
RGB_OUT17 H1-31 Output video bit 17