Datasheet

MAX9247
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
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Functional Diagram
MAX9247
TIMING AND CONTROL
DC BALANCE/
ENCODE
INPUT LATCH
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
1
0
OUT+
OUT-
PLL
PAR-TO-SER
CMF
PRE
OUT-
V
OD
V
OS
GND
R
L
/2
R
L
/2
OUT+
OUT-
OUT+
(OUT+) - (OUT-)
V
OS
(-) V
OS
(+)
((OUT+) + (OUT-))/2
V
OS
(-)
V
OD
(-)
V
OD
(-)
V
OD
= 0V
∆V
OS
= |V
OS
(+) - V
OS
(-)|
∆V
OD
= |V
OD
(+) - V
OD
(-)|
V
OD
(+)
Figure 1. LVDS DC Output Load and Parameters