Datasheet

MAX9247
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
10 ______________________________________________________________________________________
Detailed Description
The MAX9247 DC-balanced serializer operates at a
2.5MHz-to-42MHz parallel clock frequency, serializing
18 bits of parallel video data RGB_IN[17:0] when the
data-enable input DE_IN is high, or 9 bits of parallel
control data CNTL_IN[8:0] when DE_IN is low. The
RGB video input data are encoded using 2 overhead
bits, EN0 and EN1, resulting in a serial word length of
20 bits (see Table 1). Control inputs are mapped to 19
bits and encoded with 1 overhead bit, EN0, also result-
ing in a 20-bit serial word. Encoding reduces EMI and
maintains DC balance across the serial cable. Two
transition words, which contain a unique bit sequence,
are inserted at the transition boundaries of video-to-
control and control-to-video phases.
Control data inputs C0 to C4 are mapped to 3 bits each
in the serial control word (see Table 2). At the deserial-
izer, 2 or 3 bits at the same state determine the state of
the recovered bit, providing single-bit-error tolerance
for C0 to C4. Control data that may be visible if an error
occurs, such as VSYNC and HSYNC, can be connect-
ed to these inputs. Control data inputs C5 to C8 are
mapped to 1 bit each.
OUT-
OUT+
((OUT+) + (OUT-))/2
V
OS(P-P)
V
OS(P-P)
012345678910111213141516171819
EN0 EN1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17
Figure 8. Peak-to-Peak Output Offset Voltage
Bit 0 is the LSB and is serialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.
Table 1. Serial Video Phase Word Format
012345678910111213141516171819
E N 0C0C0C0C1C1C1C2C2C2C3C3C3C4C4C4C5C6C7C8
Bit 0 is the LSB and is serialized first. C[8:0] are the control inputs.
Table 2. Serial Control Phase Word Format