Datasheet

MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
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Test Circuits/Timing Diagrams (continued)
V
ID
= 0V
1.5V
RCCD
RxCLKIN_
RxCLKOUT
RCIP
Figure 6a. Clock-IN to Clock-OUT Delay (MAX9244/MAX9246/
MAX9254)
V
CC
RxCLKIN_
RxCLKOUT
PWRDWN
3V
2V
RPLLS
HIGH IMPEDANCE
1.5V
Figure 7. Phase-Locked-Loop Set Time
1.5V
PWRDWN
RxCLKIN_
RxOUT_
RxCLKOUT
RPDD
HIGH IMPEDANCE
1.5V
Figure 8. Power-Down Delay
RxCLKIN_
RxCLKOUT
+
-
RCCD
1.5V
V
ID
= 0V
RCIP
Figure 6b. Clock-IN to Clock-OUT Delay (MAX9242)
RxOUT_
RxCLKOUT
RCOP
RCOH RCOL
2.0V
0.8V
2.0V
0.8V
2.0V 2.0V
0.8V 0.8V 0.8V
RHRCRSRC
Figure 5b. Falling-Edge Output Setup/Hold and High/Low Times