Datasheet

MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
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spread-spectrum PLL locks immediately after (see
Figure 16). If the spread-spectrum PLL loses lock, it
locks again with only one PLL lock delay (see Figure 17).
AC-Coupling Benefits
Bit errors experienced with DC-coupling (Figure 18)
can be eliminated by increasing the receiver common-
mode voltage range through AC-coupling. AC-coupling
increases the common-mode voltage range of an LVDS
receiver to nearly the voltage rating of the capacitor. The
typical LVDS driver output is 350mV centered on a 1.25V
offset voltage, making single-ended output voltages of
1.425V and 1.075V. An LVDS receiver accepts signals
from 0V to 2.4V, allowing approximately ±1V common-
mode difference between the driver and receiver on a
RPLLS2 (32,800 x RCIP)
±2% OR ±4% SPREAD±4% OR ±2% SPREAD
LOW
SSG
RxCLKOUT
RxOUT_
Figure 13. Output Waveforms when Spread Amount is Changed
RPLLS2 (32,800 x RCIP)
±2% OR ±4% SPREAD
LOW
NO SPREADSSG
RxCLKOUT
RxOUT_
Figure 14. Output Waveforms when Spread is Added
RPLLS2 (32,800 x RCIP)
NO SPREAD±4% OR ±2% SPREADSSG
RxCLKOUT
RxOUT_
DATA SWITCHING BUT NOT VALID
Figure 15. Output Waveforms when Spread is Removed