Datasheet

MAX9234/MAX9236/MAX9238
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
8
Maxim Integrated
IDEAL
MIN MAX
INTERNAL STROBE
IDEAL
RSKM RSKM
IDEAL SERIAL BIT TIME
1.3V
1.1V
Figure 4. LVDS Receiver Input Skew Margin
RxOUT_
RxCLK OUT
RCIP
RCOHRCOL
2.0V
0.8V
2.0V
0.8V
2.0V
2.0V
2.0V
0.8V 0.8V
RHRCRSRC
Figure 5a. MAX9234 Output Setup/Hold and High/Low Times
RxOUT_
RxCLK OUT
RCIP
RCOH RCOL
2.0V
0.8V
2.0V
0.8V
2.0V 2.0V
0.8V 0.8V 0.8V
RHRCRSRC
Figure 5b. MAX9236/MAX9238 Output Setup/Hold and High/Low
Times
V
ID
= 0
1.5V
RCCD
RxCLK IN
RxCLK OUT
Figure 6a. MAX9234 Clock-IN to Clock-OUT Delay
RxCLK IN
RxCLK OUT
+
-
RCCD
1.5V
V
ID
= 0
Figure 6b. MAX9236/MAX9238 Clock-IN to Clock-OUT Delay
90%90%
10%10%
CHLTCLHT
RxOUT_ OR
RxCLK OUT
RxOUT_ OR
RxCLK OUT
8pF
Figure 3. Output Load and Transition Times
PWRDWN
V
CC
RxCLK IN
RxCLK OUT
3V
2V
RPLLS
HIGH-Z
Figure 7. Phase-Locked Loop Set Time