Datasheet

MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
6 _______________________________________________________________________________________
Functional Diagram
MAX9217
TIMING AND CONTROL
DC BALANCE/
ENCODE
INPUT LATCH
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
1
0
OUT+
OUT-
CMF
PLL
PAR-TO-SER
OUT-
V
OD
V
OS
GND
R
L
/ 2
R
L
/ 2
OUT+
OUT-
OUT+
(OUT+) - (OUT-)
V
OS
(-) V
OS
(+)
((OUT+) + (OUT-)) / 2
V
OS
(-)
V
OD
(-)
V
OD
(-)
V
OD
= 0V
ΔV
OS
= |V
OS
(+) - V
OS
(-)|
ΔV
OD
= |V
OD
(+) - V
OD
(-)|
V
OD
(+)
Figure 1. LVDS DC Output Load and Parameters