Datasheet

MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
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Pin Description
PIN
TSSOP TQFN
NAME FUNCTION
1, 3, 4, 44, 45, 47, 48, 38, 39, 41, 42, 43, 45, 46 TxIN0–TxIN6
5V Tolerant LVTTL/LVCMOS Channel 0 Data Inputs.
Internally pulled down to GND.
2, 8, 14, 21 2, 8, 15, 44 V
CC
Digital Supply Voltage
5, 11, 17, 24, 46 5, 11, 18, 40, 47 GND Ground
6, 7, 9, 10, 12, 13, 15 1, 3, 4, 6, 7, 9, 48 TxIN7–TxIN13
5V Tolerant LVTTL/LVCMOS Channel 1 Data Inputs.
Internally pulled down to GND.
16, 18, 19, 20, 22, 23, 25 10, 12, 13, 14, 16, 17, 19 TxIN14–TxIN20
5V Tolerant LVTTL/LVCMOS Channel 2 Data Inputs.
Internally pulled down to GND.
26 20 TxCLK IN
5V Tolerant LVTTL/LVCMOS Parallel Rate Clock Input.
Internally pulled down to GND.
27 21 PWRDWN
5V Tolerant LVTTL/LVCMOS Power-Down Input. Internally
pulled down to GND. Outputs are high impedance when
PWRDWN = low or open.
28, 30 22, 24 PLL GND PLL Ground
29 23 PLL V
CC
PLL Supply Voltage
31, 36, 42 25, 30, 36 LVDS GND LVDS Ground
32 26 TxCLK OUT+ Noninverting LVDS Parallel Rate Clock Output
33 27 TxCLK OUT- Inverting LVDS Parallel Rate Clock Output
34 28 TxOUT2+ Noninverting Channel 2 LVDS Serial Data Output
35 29 TxOUT2- Inverting Channel 2 LVDS Serial Data Output
37 31 LVDS V
CC
LVDS Supply Voltage
38 32 TxOUT1+ Noninverting Channel 1 LVDS Serial Data Output
39 33 TxOUT1- Inverting Channel 1 LVDS Serial Data Output
40 34 TxOUT0+ Noninverting Channel 0 LVDS Serial Data Output
41 35 TxOUT0- Inverting Channel 0 LVDS Serial Data Output
43 37 DCB/NC
LVTTL/LVCMOS DC-Balance Programming Input:
MAX9209: pulled up to V
CC
MAX9213: pulled up to V
CC
See Table 1.
— — EP Exposed Paddle (TQFN Only). Solder to ground.