Datasheet

MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
14 ______________________________________________________________________________________
Applications Information
Selection of AC-Coupling Capacitors
Voltage droop and the DSV of transmitted symbols
cause signal transitions to start from different voltage
levels. Because the transition time is finite, starting the
signal transition from different voltage levels causes
timing jitter. The time constant for an AC-coupled link
needs to be chosen to reduce droop and jitter to an
acceptable level.
The RC network for an AC-coupled link consists of the
LVDS receiver termination resistor (R
T
), the LVDS driver
output resistor (R
O
), and the series AC-coupling capac-
itors (C). The RC time constant for two equal-value
series capacitors is (C x (R
T
+ R
O
)) / 2 (Figure 14). The
RC time constant for four equal-value series capacitors
is (C x (R
T
+ R
O
)) / 4 (Figure 15).
R
T
is required to match the transmission line imped-
ance (usually 100Ω) and R
O
is determined by the LVDS
driver design, with a minimum value of 78Ω (see the DC
Electrical Characteristics table). This leaves the capaci-
tor selection to change the system time constant.
In the following example, the capacitor value for a
droop of 2% is calculated. Jitter due to this droop is
then calculated assuming a 1ns transition time:
C = -(2 x t
B
x DSV) / (ln (1 - D) x (R
T
+ R
O
)) (Eq 1)
where:
C = AC-coupling capacitor (F)
t
B
= bit time (s)
DSV = digital sum variation (integer)
ln = natural log
D = droop (% of signal amplitude)
R
T
= termination resistor (Ω)
(7 + 2):1
1:(9 - 2)
7
7
R
T
=
100Ω
R
T
=
100Ω
R
T
=
100Ω
R
T
=
100Ω
(7 + 2):1
1:(9 - 2)
7
7
(7 + 2):1
1:(9 - 2)
7
7
PLL
PLL
MAX9209
MAX9213
MAX9210
MAX9214
TxOUT
TxCLK OUT
RxIN
RxCLK IN
21:3 SERIALIZER 3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT
PWRDWN
TxCLK IN
TxIN
HIGH-FREQUENCY CERAMIC
SURFACE-MOUNT CAPACITORS
R
O
R
O
R
O
R
O
Figure 15. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode