Datasheet

MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
______________________________________________________________________________________ 11
To obtain DC balance on the data channels, the paral-
lel input data is inverted or not inverted, depending on
the sign of the digital sum at the word boundary. Two
complementary bits are appended to each group of 7
parallel input data bits to indicate to the MAX9210/
MAX9214 deserializers whether the data bits are invert-
ed (Figure 11). The deserializer restores the original
state of the parallel data. The LVDS clock signal alter-
nates duty cycles of 4/9 and 5/9, which maintains DC
balance. Figure 12 shows the non-DC-balanced mode
inputs mapped to LVDS outputs.
DCA0
DCB1DCA1
DCB2DCA2
CYCLE N + 1CYCLE NCYCLE N - 1
TxIN2TxIN6 TxIN3TxIN4TxIN5
TxIN9TxIN13 TxIN10TxIN11TxIN12
TxIN2TxIN3TxIN4DCA0 TxIN5TxIN6DCB0
TxIN9TxIN10TxIN11DCA1 TxIN12TxIN13DCB1
TxIN16TxIN17TxIN18DCA2 TxIN19TxIN20DCB2
TxIN0TxIN1
TxIN7TxIN8
TxIN14TxIN15TxIN16TxIN20 TxIN17TxIN18TxIN19
DCB0
TxCLK OUT-
TxOUT1
TxOUT0
TxOUT2
TxIN1
TxIN8
TxIN15
TxIN0
TxIN7
TxIN14
TxCLK OUT+
Figure 11. DC-Balanced Mode Inputs Mapped to LVDS Outputs
2.0V
3.0V
HIGH-Z
DIFFERENTIAL 0
3.6V
V
OD
= 0
V
CC
TxOUT_, TxCLK OUT
TxCLK IN
PWRDWN
TPPLS
Figure 9. PLL Set Time
TxOUT_, TxCLK OUT
TxCLK IN
PWRDWN
HIGH-Z
0.8V
TPDD
Figure 10. Power-Down Delay