Datasheet

MAX9205/MAX9207
10-Bit Bus LVDS Serializers
9
Maxim Integrated
PWRDN
TCLK
OUT±
t
PL
ACTIVE
2.0V
0.8V
1.5V
t
HZ
OR t
LZ
t
ZH
OR t
ZL
SYNC 1 = SYNC 2 = LOW
EN = HIGH
TCLK_R/F = HIGH
HIGH IMPEDANCEHIGH IMPEDANCE
Figure 7. PLL Lock Time and PWRDN High-Impedance Delays
TCLK
OUT±
IN
IN0 - IN9 SYMBOL N
IN0 - IN9 SYMBOL N + 1
t
SD
START BIT
V
DIFF
= 0 V
DIFF
= (OUT+) - (OUT-)TCLK_ R/F = HIGH
1.5V
STOP BIT START BIT STOP BIT
OUT0 - OUT9 SYMBOL N+1
OUT0 - OUT9 SYMBOL N
TIMING SHOWN FOR TCLK_R/F = HIGH
Figure 8. Serializer Delay
(OUT+) - (OUT-)
WAVEFORM
SUPERIMPOSED RANDOM DATA
O DIFFERENTIAL
t
DJIT
Figure 9. Definition of Deterministic Jitter (t
DJIT
)
(OUT+) - (OUT-)
WAVEFORM
"CLOCK" PATTERN (1010...)
t
RJIT
t
RJIT
O DIFFERENTIAL
Figure 10. Definition of Random Jitter (t
RJIT
)