Datasheet

MAX9205/MAX9207
10-Bit Bus LVDS Serializers
8
Maxim Integrated
V
DIFF
V
DIFF
= 0
t
HLT
20%
80%
80%
20%
t
LHT
OUT+
10pF
10pF
OUT-
R
L
V
DIFF
= (OUT+) - (OUT-)
Figure 4. Output Load and Transition Times
TCLK
IN_
1.5V
1.5V1.5V
t
H
t
S
t
TCP
1.5V
TIMING SHOWN FOR TCLK_R/F = LOW
1.5V
Figure 5. Data Input Setup and Hold Times
1.5V
1.5V
t
LZ
t
HZ
t
ZL
t
ZH
3V
0
1.1V
V
OL
V
OH
OUT±
1.1V
50%50%
50%50%
EN
OUT+
OUT-
PARASITIC PACKAGE AND
TRACE CAPACITANCE
+1.1V
10pF
13.5Ω
13.5Ω
10pF
EN
Figure 6. High-Impedance Test Circuit and Timing