Datasheet

MAX9157
Quad Bus LVDS Transceiver
12 ______________________________________________________________________________________
DO_-/RIN_-
DO_+/RIN_+
RO_
50%
V
ID
V
OL
V
OH
20%20%
80% 80%
t
PHLD
t
PLHD
t
THL
t
TLH
V
CM
V
CM
50%
Figure 8. Receiver Transition Time and Propagation Delay Timing Diagram
RO_
1/4 MAX9157
C
L
INCLUDES LOAD AND TEST JIG CAPACITANCE.
S
1
= V
CC
FOR t
PZL
AND t
PLZ
MEASUREMENTS.
S
1
= GND FOR t
PZH
AND t
PHZ
MEASUREMENTS.
GENERATOR
50Ω
C
L
R
L
S
1
V
CC
DO_+/RIN_+
DO_-/RIN_-
RE_
Figure 9. Receiver High-Impedance Delay Test Circuit
RE_
RO_ WHEN
V
ID
= -100mV
RO_ WHEN
V
ID
= +100mV
50%
0.5V
0.5V
t
PLZ
t
PHZ
t
PZL
t
PZH
50%
V
CC
V
CC
V
OL
V
OH
GND
0
50%
50%
Figure 10. Receiver High-Impedance Waveforms