Datasheet

Input Fail-Safe
The differential inputs of the MAX9152 do not have
internal fail-safe biasing. If fail-safe biasing is required,
it can be implemented with external large-value resis-
tors. IN_+ should be pulled up to V
CC
with 10kΩ and
IN_ should be pulled down to GND with 10kΩ. The volt-
age-divider formed by the 10kΩ resistors and the 100Ω
termination resistor (across IN_+ and IN_-) provides a
slight positive differential bias and sets a high state at
the device output when inputs are undriven.
Output Resistance
The MAX9152 has a selectable differential output resis-
tance to reduce reflections from impedance discontinu-
ities in the interconnect. Reflections are reduced,
compared to a high-impedance output. A termination
resistor at the receiver is still required and is the primary
termination for the interconnect. Select the output resis-
tance that best matches the differential characteristic
impedance of the interconnect used.
Select Function
The SEL0 and SEL1 logic inputs allow the device to be
configured as a high-speed differential crosspoint, 2:1
mux, 1:2 demux, dual repeater, or 1:2 splitter (Figure
8). See Table 1 for mode selection settings.
Enable Function
The EN0 and EN1 logic inputs enable and disable dri-
ver outputs OUT0 and OUT1. Setting EN0 or EN1 high
enables the corresponding driver output. Setting EN0
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch
_______________________________________________________________________________________ 7
1.5V
EN0 = EN1 = HIGH
V
ID
= (V
IN_+
) − (V
IN_-
)
t
HOLD
t
SWITCH
t
SET
V
ID
= 0
V
ID
= 0
IN1 IN0
IN0+
IN0-
IN1-
IN1+
OUT_-
SEL_
OUT_+
1.5V
EN0 = EN1 = HIGH
V
ID
= (V
IN_+
) − (V
IN_-
)
t
HOLD
t
SWITCH
t
SET
V
ID
= 0
V
ID
= 0
IN0 IN1
IN0+
IN0-
IN1-
IN1+
OUT_+
SEL_
OUT_-
Figure 2. Input to Rising Edge Select Setup, Hold, and Mux Switch Timing Diagram
Figure 3. Input to Falling Edge Select Setup, Hold, and Mux Switch Timing Diagram