Datasheet
MAX9110/MAX9112
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23
6 _______________________________________________________________________________________
V
OS
V
CC
GND
DIN_
R
L
/2
R
L
/2
V
OS
V
OD
DO_-
DO_+
Figure 1. LVDS Transmitter V
OD
and V
OS
Test Circuit
R
L
C
L
DO_ +
DO_ -
C
L
50
Ω
DIN_
GENERATOR
Figure 2. Transmitter Propagation Delay and Transition Time
Test Circuit
stage presents a symmetrical, high-impedance output,
reducing differential reflection and timing distortion. The
driver outputs are short circuit current limited and enter a
high-impedance state when the device is not powered.
LVDS Operation
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled impedance medium as defined by the EIA/TIA-
644 LVDS standard. The LVDS standard uses a lower
voltage swing than other common communication stan-
dards, achieving higher data rates with reduced power
consumption while reducing EMI emissions and system
susceptibility to noise.
LVDS transmitters such as the MAX9110/MAX9112
convert CMOS/LVTTL signals to low-voltage differential
signals at rates in excess of 500Mbps. The MAX9110/
MAX9112 current-steering architecture requires a resis-
tive load to terminate the signal and complete the trans-
mission loop. Because the device switches the direc-
tion of current flow and not voltage levels, the actual
output voltage swing is determined by the value of the
termination resistor at the input of an LVDS receiver.
Logic states are determined by the direction of current
flow through the termination resistor. With a typical
3.5mA output current, the MAX9110/MAX9112 produce
an output voltage of 350mV when driving a 100Ω load.
The steady-state-voltage peak-to-peak swing is twice
the differential voltage, or 700mV (typ).
Applications Information
Supply Bypassing
Bypass V
CC
with high-frequency surface-mount ceramic
0.1µF and 0.001µF capacitors in parallel, as close to the
device as possible, with the smaller valued capacitor the
closest. For additional supply bypassing, place a 10µF
tantalum or ceramic capacitor at the point where power
enters the circuit board.
0
V
OH
V
OL
DIN_
DO_
-
DO_+
V
DIFF
3V
t
PHLD
1.5V
0
t
THL
20%
0
80%
80%
0
t
TLH
20%
0V DIFFERENTIAL
t
PLHD
1.5V
V
DIFF
= V
DO_
+ - V
DO_
-
Figure 3. Transmitter Propagation Delay and Transition Time Waveforms