Datasheet

22
Maxim Integrated
Dual-Input Linear Charger, Smart Power Selector
with Advanced Battery Temperature Monitoring
MAX8934G
+25NC). Any thermistor resistance can be used as long
as the value of R
THMSW
is equivalent to the thermistor’s
+25NC resistance. The MAX8934G THM thresholds are
optimized for a thermistor Beta of 3964. The general rela-
tion of thermistor resistance to temperature is defined by
the following equation:
11
-
T 273 C 298 C
T 25
RR e




+° °


β
= ×
where:
R
T
= The resistance in ohms of the thermistor at
temperature T in NC
R
25
= The resistance in ohms of the thermistor at
+25NC
A = The material constant of the thermistor
T = The temperature of the thermistor in NC
Charging is suspended when the thermistor temperature
is out of range (V
THM_T1
< V
THM
or V
THM
< V
THM_T4
).
The charge timers are also suspended and hold their
state but no fault is indicated. When the thermistor
comes back into range, charging resumes and the
charge timer continues from where it left off.
The THMEN input controls THMSW and the thermistor
monitor circuitry when the battery charger is disabled,
providing the user with the means to minimize the bat-
tery current drain caused by the thermistor monitor. The
THMEN input is ignored while the battery is charging,
since the thermistor must be monitored at all times.
While charging, the thermistor monitor is used to auto-
matically adjust the charge termination voltage and/or
the fast-charge current, depending on the sensed bat-
tery temperature. If the battery temperature exceeds the
THM hot overtemperature threshold and THMEN is high,
the OT flag pulls low. Typical systems connect OT to a
FP input so that the system can safely shut down.
Always-On LDO
The ultra-low quiescent current LDO is always on and is
preset to an output voltage of 3.3V. The LDO provides up
to 30mA output current. When DC and USB are invalid
and the battery is discharging, the LDO output volt-
age tracks V
SYS
as it drops below 3.3V. A 1FF ceramic
capacitor connected from LDO to GND is recommended
for most applications.
Power Dissipation
PCB Layout and Routing
Good design minimizes ground bounce and voltage
gradients in the ground plane. GND should connect to
the power-ground plane at only one point to minimize the
effects of power-ground currents. Battery ground should
connect directly to the power-ground plane. Connect
GND to the exposed pad directly under the IC. Use mul-
tiple tightly spaced vias to the ground plane under the
exposed pad to help cool the IC. Position input capaci-
tors from DC, SYS, BATT, and USB to the power-ground
plane as close as possible to the IC. Keep high current
traces such as those to DC, SYS, and BATT as short and
wide as possible. Refer to the MAX8934A Evaluation Kit
for a suitable PCB layout example.
Table 3. Package Thermal Characteristics
28-PIN 4mm x 4mm THIN QFN
SINGLE-LAYER PCB MULTILAYER PCB
Continuous Power
Dissipation
1666.7mW
(derate 20.8mW/NC above +70NC)
2285.7mW
(derate 28.6mW/NC above +70NC)
B
JA
48NC/W 35NC/W
B
JC
3NC/W 3NC/W