Datasheet

MAX8903A–E/G/H/J/N/Y
2A 1-Cell Li+ DC-DC Chargers
for USB and Adapter Power
23
Maxim Integrated
on-time constraints (t
ONMIN
), the regulator becomes a
fixed minimum on-time valley current regulator.
Versions of the MAX8903 with f
SW
= 4MHz offer the
smallest L
OUT
while delivering good efficiency with low
input voltages (5V or 9V). For applications that use high
input voltages (12V), the MAX8903G with f
SW
= 1MHz
is the best choice because of its higher efficiency.
For a given maximum output voltage, the minimum
inductor ripple current condition occurs at the lowest
input voltage that allows the regulator to maintain f
SW
operation. If the minimum input voltage dictates an off-
time less than t
OFFMIN
, then the minimum inductor rip-
ple condition occurs just before the regulator enters
fixed minimum off-time operation. To allow the current-
mode regulator to provide a low-jitter, stable duty factor
operation, the minimum inductor ripple current
(I
L_RIPPLE_MIN
) should be greater than 150mA in the
minimum inductor ripple current condition. The maxi-
mum allowed output inductance L
OUT_MAX
is therefore
obtained using the equations (1) and (2) below.
(1)
otherwise,
where t
OFF
is the off-time, V
SYS(MAX)
is maximum charger
output voltage, and V
DC(MIN)
is minimum DC input volt-
age.
(2)
where L
OUT _ MAX
is the maximum allowed inductance.
To obtain a small-sized inductor with acceptable core
loss, while providing stable, jitter-free operation at the
advertised f
SW
, the actual output inductance (L
OUT
), is
obtained by choosing an appropriate ripple factor K, and
picking an available inductor in the range inductance
yielded by equations (2), (3), and (4). L
OUT
should also
not be lower than the minimum allowable inductance as
shown in Table 6. The recommended ripple factor ranges
from (0.2 ≤ K ≤ 0.45) for (2A ≥ I
S
DLIM
≥
1A) designs.
(3)
where t
OFF
is the minimum off-time obtained from (1).
(4)
where V
DC(MAX)
is maximum input voltage, V
SYS(MIN)
is
the minimum charger output voltage, and t
ON
is the on-
time at high input voltage, as given by the following
equation:
(5)
otherwise,
The saturation current DC rating of the inductor (I
SAT
)
must be greater than the DC step-down output current
limit (I
SDLIM
) plus one-half the maximum ripple current,
as given by equation (6).
(6)
where IL
RIPPLE_MAX
is the greater of the ripple currents
obtained from (7) and (8).
(7)
(8)
PCB Layout and Routing
Good design minimizes ground bounce and voltage gra-
dients in the ground plane, which can result in instability
or regulation errors. The GND and PGs should connect to
the power-ground plane at only one point to minimize the
effects of power-ground currents. Battery ground should
connect directly to the power-ground plane. The ISET
and IDC current-setting resistors should connect directly
to GND to avoid current errors. Connect GND to the
exposed pad directly under the IC. Use multiple tightly
spaced vias to the ground plane under the exposed pad
to help cool the IC. Position input capacitors from DC,
SYS, BAT, and USB to the power-ground plane as close
as possible to the IC. Keep high current traces such as
those to DC, SYS, and BAT as short and wide as possi-
ble. Refer to the MAX8903A Evaluation Kit for a suitable
PCB layout example.
IL
VV t
L
RIPPLE MIN T
DC MAX SYS MIN ON
O
ON
__
() ()
=
()
×−
UUT
IL
Vt
L
RIPPLE MIN T
SYS MAX OFF
OUT
OFF
__
()
=
×
II
IL
SAT SDLIM
RIPPLE MAX
>+
_
2
⎝
=×t
V
Vf
ON
SYS MIN
DC MAX SW
()
()
1
tt if
V
Vf
ON ONMIN
SYS MIN
DC MAX SW
=×
⎛
⎝
⎜
⎞
⎠
⎟
()
()
1
≤≤ t
ONMIN
,
L
VV t
K
OUT MIN t
DC MAX SYS MIN ON
ON
__
() ()
=
()
×
×
−
II
SDLIM
L
Vt
KI
OUT MIN T
SYS MAX OFF
SDLIM
OFF
__
()
=
×
×
L
Vt
I
OUT MAX
SYS MAX OFF
L RIPPLE MIN
_
()
__
=
×
=
⎛
⎝
−1t
V
V
OFF
SYS MAX
DC MIN
()
()
⎜⎜
⎞
⎠
⎟
×
1
f
SW
tt if
V
V
OFF OFFMIN
SYS MAX
DC MIN
=
⎛
⎝
⎜
⎞
⎠
⎟
−
()
()
1 ××≤
1
f
t
SW
OFFMIN
,