Datasheet

31Maxim Integrated
1.2A Switch-Mode Li+ Chargers with ±22V Input
Rating and JEITA Battery Temperature Monitoring
MAX8900A/MAX8900B/MAX8900C
impedance), the voltage spike could be twice that of
the nominal source voltage. In other words, a 6V source
with a high-Q LC tank circuit in the cabling can result in
a voltage spike as high as 12V. The MAX8900_’s high
input absolute maximum voltage rating of +22V to -22V
eliminates any concerns about the voltage spikes due to
inductive kicking for many applications.
In the event that an application may see a high-Q LC
tank circuit in the cabling for a supply that is > +11V, a
resistor (R
IN
) must be added in series with C
IN
to reduce
the Q of the tank circuit. The resistor value can be found
experimentally by assuming the parasitic inductance
(L
PAR
) of the input cabling is 1FH/m, then use the follow-
ing equation give a good starting value for R
IN
:
PAR
IN
IN
L
R2
C
= ×
An alternative method for estimating L
PAR
is to measure
the frequency of the input voltage spike ringing and then
calculate L
PAR
from the following equation.
( )
PAR
R IN
1
L
2 fC
=
×π× ×
Overvoltage and Reverse Input Voltage Protection
The MAX8900_ provides for a +22V absolute maximum
positive input voltage and a -22V absolute maximum
negative input voltage. Excursions to the absolute maxi-
mum voltage levels should be on a transient basis only,
but can be withstood by the MAX8900_ indefinitely.
Situations that typically require extended input voltage
ratings include but are not limited to the following:
U Inductive kick
U Charge source failure
U Power surge
U Improperly wired wall adapter
U Improperly set universal wall adapter
U Wall adapter with the correct plug, but wrong voltage
U Home-built computer with USB wiring harness con-
nected backwards (negative voltage)
U USB connector failure
U Excessive ripple voltage on a switch-mode wall charger
U USB powered hub that is powered by a wall charger
(typically through a barrel connector) that has any of
the aforementioned issues
U Unregulated charger (passively regulated by the
turns ratio of the magnetic’s turns ratio)
PCB Layout
The MAX8900_ WLP package and bump configuration
allows for a small-size low-cost PCB design. Figures 3
and 14 show that the MAX8900_ package’s 30 bumps are
combined into 18 functional nodes. The bump configura-
tion places all like nodes adjacent to each other to mini-
mize the area required for routing. The bump configuration
also allows for a layout that does not use any vias within the
WLP bump matrix (i.e., no micro vias). To utilize this no via
layout, CEN is left unconnected and the STAT3 pin is not
used (2-pin status version).
Figure 15 shows the recommended land pattern for the
MAX8900_. Figure 16 shows the cross section of the
MAX8900_’s bump with detail of the under-bump metal
(UBM). The diameter of each pad in the land pattern is
close to the diameter of the UBM. This land pattern to UBM
relationship is important to get the proper reflow of each
solder bump.
Underfill is not necessary for the MAX8900_’s package to
pass the JESD22-B111 Board Level Drop Test Method for
Handheld Electronic Products. JESD22-B111 covers end
applications such as cell phones, PDAs, cameras, and
other products that are more prone to being dropped dur-
ing their lifetime due to their size and weight. Please con-
sider using underfill for applications that require higher reli-
ability than what is covered in the JESD22-B111 standard.
Careful printed circuit layout is important for minimizing
ground bounce and noise. Figure 14 is an example layout
of the critical power components for the MAX8900_. The
arrangement of the components that are not shown in
Figure 14 is less critical. Refer to the MAX8900 Evaluation
Kit for a complete PCB layout example. Use the following
list of guidelines in addition to Application Note 1891:
Wafer-Level Packaging (WLP) and Its Applications (www.
maximintegrated.com/ucsp) to layout the MAX8900_
PCB.