Datasheet
MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down Regulators
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Pin Description
PIN NAME FUNCTION
1 PWRGD1
Power-Good Open-Drain Output for Regulator 1. PWRGD1 is high impedance when V
REFIN
≥ 0.54V and
V
FB1
≥ 0.9 x V
REFIN
. PWRGD1 is low when V
REFIN
< 0.54V, EN1 is low, V
DD
or IN1 is below UVLO, the
thermal shutdown is activated, or when V
FB1
< 0.9 x V
REFIN
.
2 REFIN
External Reference Input for Regulator 1. Connect an external reference to REFIN, or connect REFIN to SS1
to use the internal reference. REFIN is discharged to GND through 335Ω when EN1 is low or regulator 1 is
shut down due to a fault condition.
3V
DD
Supply Voltage. Connect a 10Ω resistor from V
DD
to VDL and connect a 0.1μF capacitor from V
DD
to GND.
4 GND
Analog Ground. Connect GND to the analog ground plane. Connect the analog and power ground planes
together at a single point near the IC.
5 N.C. No Connection
6 VDL
Supply Voltage Input for Low-Side Gate Drive. Connect VDL to IN_ or the highest available supply voltage
less than 3.6V. Connect a 1μF capacitor from VDL to the power ground plane.
7 FSYNC
Frequency Set and Synchronization. Connect a 4.75kΩ to 20.5kΩ resistor from FSYNC to GND to set the
switching frequency or drive with a 250kHz to 2.5MHz clock signal to synchronize switching.
R
FSYNC
= (T - 0.05μs) x (10kΩ/0.95μs), where T is the oscillator period.
8 PWRGD2
Power-Good Open-Drain Output for Regulator 2. PWRGD2 is high impedance when V
SS2
≥ 0.54V and V
FB2
≥ 0.9 x V
SS2
. PWRGD2 is low when V
SS2
< 0.54V, EN2 is low, V
DD
or IN2 is below UVLO, the thermal
shutdown is activated, or when V
FB2
< 0.9 x V
SS2
.
9 SS2
S oft- S tar t for Reg ul ator 2. C onnect a cap aci tor fr om S S 2 to GN D to set the soft- star t ti m e. S ee the S etti ng the S oft-
S tar t Ti m e secti on. S S 2 i s i nter nal l y p ul l ed l ow w i th 335Ω w hen E N 2 i s l ow or r eg ul ator 2 i s i n a faul t cond i ti on.
10 FB2
Feedback Input for Regulator 2. Connect FB2 to the center of an external resistor-divider from the output to
GND to set the output voltage from 0.6V to 90% of V
IN2
. FB2 is high impedance when the IC is shut down.
11 COMP2
Compensation for Regulator 2. COMP2 is the output of the internal voltage-error amplifier. Connect external
compensation network from COMP2 to FB2. See the Compensation Design section. COMP2 is internally
pulled to GND when the output is shut down.
12 EN2
Enable Input for Regulator 2. Drive EN2 high to enable regulator 2, or drive low for shutdown. For always-on
operation, connect EN2 to V
DD
.
13, 14 IN2
Power-Supply Input for Regulator 2. The voltage range is 2.35V (MAX8855A) to 3.6V. Connect two 10μF and
one 0.1μF ceramic capacitors from IN2 to PGND2.
15, 16, 17 PGND2
Power Ground for Regulator 2. Connect all PGND_ pins to the power ground plane. Connect the power
ground and analog ground planes together at a single point near the IC.
18, 19 LX2
Inductor Connection for Regulator 2. Connect an inductor between LX2 and the regulator output. LX2 is high
impedance when the IC is shut down.
20 BST2
Bootstrap Connection for Regulator 2. Connect a 0.1μF capacitor from BST2 to LX2. BST2 is the supply for
the high-side gate drive. BST2 is charged from VDL with an internal pMOS switch. In shutdown, there is an
internal diode junction from LX2 to BST2 and from VDL to BST2.
21 BST1
Bootstrap Connection for Regulator 1. Connect a 0.1μF capacitor from BST1 to LX1. BST1 is the supply for
the high-side gate drive. BST1 is charged from VDL with an internal pMOS switch. In shutdown, there is an
internal diode junction from LX1 to BST1 and from VDL to BST1.
22, 23 LX1
Inductor Connection for Regulator 1. Connect an inductor between LX1 and the regulator output. LX1 is high
impedance when the IC is shut down.
24, 25, 26 PGND1
Power Ground for Regulator 1. Connect all PGND_ pins to the power ground plane. Connect the power
ground and analog ground planes together at a single point near the IC.