Datasheet

Output-Capacitor Selection
The key selection parameters for the output capacitor
are capacitance, ESR, ESL, and voltage-rating require-
ments. These affect the overall stability, output ripple
voltage, and transient response of the DC-DC convert-
er. The output ripple occurs due to variations in the
charge stored in the output capacitor, the voltage drop
due to the capacitor’s ESR, and the voltage drop due to
the capacitor’s ESL. Calculate the output-voltage ripple
due to the output capacitance, ESR, and ESL as:
where the output ripple due to output capacitance,
ESR, and ESL is:
or:
whichever is greater.
It should be noted that the above ripple voltage compo-
nents add vectrorially rather than algebraically, thus
making V
RIPPLE
a conservative estimate.
The peak inductor current (I
P-P
) is:
Use these equations for initial capacitor selection.
Determine final values by testing a prototype or an eval-
uation circuit. A smaller ripple current results in less out-
put-voltage ripple. Since the inductor ripple current is a
function of the inductor value, the output-voltage ripple
decreases with larger inductance. Use ceramic capaci-
tors for low ESR and low ESL at the switching frequency
of the converter. The low ESL of ceramic capacitors
makes ripple voltages due to ESL negligible.
Load-transient response depends on the selected out-
put capacitance. During a load transient, the output
instantly changes by ESR x ΔI
LOAD
. Before the con-
troller can respond, the output deviates further,
depending on the inductor and output capacitor values.
After a short time, the controller responds by regulating
the output voltage back to its predetermined value. The
controller response time depends on the closed-loop
bandwidth. A higher bandwidth yields a faster
response time, preventing the output from deviating fur-
ther from its regulating value. See the
Compensation
Design
and
Safe-Starting into a Prebiased Output
sec-
tions for more details.
Compensation Design
The power-stage transfer function consists of one dou-
ble pole and one zero. The double pole is introduced
by the output filtering inductor, L, and the output filter-
ing capacitor, C
O
. The ESR of the output filtering
capacitor determines the zero. The double pole and
zero frequencies are given as follows:
where R
L
is equal to the sum of the output inductor’s
DC resistance and the internal switch resistance,
R
DS(ON)
. A typical value for R
DS(ON)
is 35mΩ. R
O
is the
output load resistance, which is equal to the rated out-
put voltage divided by the rated output current. ESR is
the total ESR of the output-filtering capacitor. If there is
more than one output capacitor of the same type in par-
allel, the value of the ESR in the above equation is
equal to that of the ESR of a single-output capacitor
divided by the total number of output capacitors.
The high-switching-frequency range of the MAX8855/
MAX8855A allows the use of ceramic output capacitors.
Since the ESR of ceramic capacitors is typically very
low, the frequency of the associated transfer-function
zero is higher than the unity-gain crossover frequency,
f
C
, and the zero cannot be used to compensate for the
double pole created by the output filtering inductor and
capacitor. The double pole produces a gain drop of
40dB and a phase shift of 180° per decade. The error
amplifier must compensate for this gain drop and phase
shift to achieve a stable high-bandwidth closed-loop
system. Therefore, use type III compensation as shown
in Figure 4. Type III compensation possesses three
poles and two zeros with the first pole, f
P1_EA
, located at
0Hz (DC). Locations of other poles and zeros of type III
compensation are given by:
f
RC
ZEA1
1
279
_
=
××π
f
ESR C
Z ESR
O
_
=
××
1
2π
ff
LC
R ESR
RR
PLC P LC
O
O
OL
12
1
2
__
==
×× ×
+
+
π
I
VV
fL
V
V
PP
IN OUT
S
OUT
IN
=
×
×
V
I
t
ESL
RIPPLE ESL
PP
OFF
()
V
I
t
ESL
RIPPLE ESL
PP
ON
()
V I ESR
RIPPLE ESR P P()
V
I
Cf
RIPPLE C
PP
OUT S
()
=
××
8
VV V V
RIPPLE RIPPLE C RIPPLE ESR RIPPLE ESL
=+ +
() ( ) ( )
MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down Regulators
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