Datasheet

Sequencing is achieved by connecting EN2 to
PWRGD1. In this mode, regulator 2 starts once regulator
1 reaches regulation.
In Figure 3d, EN1 and EN2 are connected together and
driven as a single input. Although both outputs begin
ramping up at the same time, slope matching is
achieved by selecting the SS_ capacitors. See the
Setting the Soft-Start Time section for information on
selecting the SS_ capacitors. In Figure 3d, the slope of
the output voltages during soft-start is equal. This is
achieved by setting the ratio of the soft-start capacitors
equal to the ratio of the output voltages:
Synchronization (FSYNC)
The MAX8855/MAX8855A operate from 500kHz to
2MHz using either its internal oscillator, or an externally
supplied clock. See the Setting the Switching
Frequency section.
Thermal-Overload Protection
Thermal-overload protection limits the total power dissi-
pation of the MAX8855/MAX8855A. Internal thermal sen-
sors monitor the junction temperature at each of the
regulators. When the junction temperature exceeds
+165°C, the corresponding regulator is shut down,
allowing the IC to cool. The thermal sensor turns the reg-
ulator on after the junction temperature cools by +20°C.
In a continuous thermal-overload condition, this results in
a pulsed output.
Design Procedure
Setting the Output Voltage
The output voltages for regulator 1 (with REFIN con-
nected to SS1) and regulator 2 are set with a resistor
voltage-divider connected from the output to FB_ to
GND as shown in Figure 4. Select a value for the resis-
tor connected from output to FB_ (R4 in Figure 4)
between 2kΩ and 10kΩ. Use the following equations to
find the value for the resistor connected from FB_ to
GND (R6 in Figure 4):
R
V
R
OUT
6
06
06
4=
−
()
×
.
.
_
C
C
V
V
SS
SS
OUT
OUT
1
2
1
2
=
MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down Regulators
12 ______________________________________________________________________________________
Figure 3d. Startup and Sequencing Options—Matching Startup Slopes of Output Voltages with Internal Reference
EN
OUT1
OUT2
PWRGD2
PWRGD1
EN
EN1
SS2
PWRGD1
EN2
SS1
PWRGD2
V
DD
REFIN
10kΩ
10kΩ
Figure 4. Type III Compensation Network
LX_
FB_
COMP_
C
O
R4
R6
R7
C9
C11
L
OUTPUT
R8
C10
MAX8855/
MAX8855A