Datasheet

MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
______________________________________________________________________________________ 17
QR
S
RESET DOMINANT
CURRENT
SENSE
Σ
OSCILLATOR
SLOPE COMP
CLOCK
LX
PGND
FB
COMP
1.233V
1.14V
SOFT-
START
V
LIMIT
PWM
COMPARATOR
FAULT
COMPARATOR
ILIM
COMPARATOR
TO FAULT LATCH
ERROR AMP
Figure 3. Step-Up Regulator Functional Diagram
voltage, the controller resets the flip-flop and turns off
the MOSFET. Since the inductor current is continuous,
a transverse potential develops across the inductor that
turns on the diode (D1). The voltage across the induc-
tor then becomes the difference between the output
voltage and the input voltage. This discharge condition
forces the current through the inductor to ramp back
down, transferring the energy stored in the magnetic
field to the output capacitor and the load. The MOSFET
remains off for the rest of the clock cycle.
Gate-On Linear-Regulator Controller, REG P
The gate-on linear-regulator controller (REG P) is an
analog gain block with an open-drain n-channel output.
It drives an external pnp pass transistor with a 6.8kΩ
base-to-emitter resistor (Figure 1). Its guaranteed base-
drive sink current is at least 1mA. The regulator including
Q1 in Figure 1 uses a 0.47µF ceramic output capacitor
and is designed to deliver 20mA at 25V. Other output
voltages and currents are possible with the proper pass
transistor and output capacitor. See the Pass-Transistor
Selection and Stability Requirements sections.
REG P is typically used to provide the TFT-LCD gate
drivers’ gate-on voltage. Use a charge pump with as
many stages as necessary to obtain a voltage exceed-
ing the required gate-on voltage (see the Selecting the
Number of Charge-Pump Stages section). Note the
voltage rating of DRVP is 36V. If the charge-pump out-
put voltage can exceed 36V, an external cascode npn
transistor should be added as shown in Figure 4.
Alternately, the linear regulator can control an interme-
diate charge-pump stage while regulating the final
charge-pump output (Figure 5).
MAX8795A
DRVP
FBP
V
MAIN
FROM CHARGE-PUMP
OUTPUT
npn CASCODE
TRANSISTOR
pnp PASS
TRANSISTOR
V
GON
Figure 4. Using Cascoded npn for Charge-Pump Output
Voltages > 36V
MAX8795A
DRVP
FBP
V
GON
35V
LX
V
MAIN
14V
0.22µF
0.1µF
0.1µF
0.47µF
47pF
150pF
274kΩ
1%
10.2kΩ
1%
6.8kΩ
68pF
Q1
Figure 5. The linear regulator controls the intermediate charge-
pump stage.