Datasheet

MAX8792
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
______________________________________________________________________________________ 25
rough estimate and is no substitute for breadboard
evaluation, preferably including verification using a
thermocouple mounted on N
H
:
where C
OSS
is the N
H
MOSFET’s output capacitance,
Q
G(SW)
is the charge needed to turn on the N
H
MOS-
FET, and I
GATE
is the peak gate-drive source/sink cur-
rent (2.2A typ).
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the C
x V
IN
2
x f
SW
switching-loss equation. If the high-side
MOSFET chosen for adequate R
DS(ON)
at low battery
voltages becomes extraordinarily hot when biased from
V
IN(MAX)
, consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (N
L
), the worst-case power
dissipation always occurs at maximum input voltage:
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
I
LOAD(MAX)
, but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can “overdesign” the
circuit to tolerate:
where I
VALLEY(MAX)
is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good size heatsink to handle the overload
power dissipation.
Choose a Schottky diode (D
L
) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. Select a
diode that can handle the load current during the dead
times. This diode is optional and can be removed if effi-
ciency is not critical.
Boost Capacitors
The boost capacitors (C
BST
) must be selected large
enough to handle the gate charging requirements of
the high-side MOSFETs. Typically, 0.1μF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side, MOSFETs require
boost capacitors larger than 0.1μF. For these applica-
tions, select the boost capacitors to avoid discharging
the capacitor more than 200mV while charging the
high-side MOSFETs’ gates:
where N is the number of high-side MOSFETs used for
one regulator, and Q
GATE
is the gate charge specified
in the MOSFET’s data sheet. For example, assume (2)
IRF7811W n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a sin-
gle IRF7811W has a maximum gate charge of 24nC
(V
GS
= 5V). Using the above equation, the required
boost capacitance would be:
Selecting the closest standard value, this example
requires a 0.22μF ceramic capacitor.
Minimum Input-Voltage Requirements
and Dropout Performance
The output voltage-adjustable range for continuous-
conduction operation is restricted by the nonadjustable
minimum off-time one-shot. For best dropout perfor-
mance, use the slower (200kHz) on-time settings. When
working with low-input voltages, the duty-factor limit
must be calculated using worst-case values for on- and
off-times. Manufacturing tolerances and internal propa-
gation delays introduce an error to the on-times. This
error is greater at higher frequencies. Also, keep in
mind that transient response performance of buck reg-
ulators operated too close to dropout is poor, and bulk
output capacitance must often be added (see the V
SAG
equation in the Quick-PWM Design Procedure section).
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (ΔI
DOWN
)
as much as it ramps up during the on-time (ΔI
UP
). The
ratio h = ΔI
UP
/ΔI
DOWN
is an indicator of the ability to
slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
each switching cycle and V
SAG
greatly increases
unless additional output capacitance is used.
C
nC
mV
F
BST
=
×
=
224
200
024. μ
C
NQ
mV
BST
GATE
=
×
200
II
I
I
I LIR
LOAD VALLEY MAX
L
VALLEY MAX
LOAD MAX
=+
=+
⎛
⎝
⎜
⎞
⎠
⎟
()
()
()
Δ
2
2
PD N sistive
V
V
IR
L
OUT
IN MAX
LOAD DS ON
( Re )
()
()
=−
⎛
⎝
⎜
⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
()
1
2
PD N Switching V I f
Q
I
CVf
H IN MAX LOAD SW
GSW
GATE
OSS IN SW
( )
()
()
=
⎛
⎝
⎜
⎞
⎠
⎟
+
2
2