Datasheet
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
______________________________________________________________________________________ 21
be less than or equal to 1/5 the switching frequency.
Select a value for f
C
in the range:
The feedback voltage-divider gain (V
REF
/V
OUT
) should
be included for an output voltage higher than 3.3V,
where V
REFIN
is equal to 3.3V.
At the crossover frequency, the total loop gain must
equal 1, and is expressed as:
For the case where f
zMOD
is greater than f
C
:
Then R
C
can be calculated as:
where g
mEA
= 1.7mS.
The error-amplifier compensation zero formed by R
C
and C
C
should be set at the modulator pole f
PMOD
.
Calculate the value of C
C
as follows:
If f
PMOD
is less than 5 x f
C
, add a second capacitor C
F
from COMP to GND. The value of C
F
is:
As the load current decreases, the modulator pole also
decreases; however, the modulator gain increases
accordingly and the crossover frequency remains the
same.
For the case where f
zMOD
is less than f
C
:
The power modulator gain at f
C
is:
The error-amplifier gain at f
C
is:
R
C
is calculated as:
where g
mEA
= 1.7mS.
C
C
is calculated from:
C
F
is calculated from:
The current-mode control model on which the above
design procedure is based requires an additional high-
frequency term, G
S
(s), to account for the effect of sam-
pling the peak inductor current. The term G
S
(s) produces
additional phase lag at crossover and should be modeled
to estimate the phase margin obtainable by the selected
compensation components. As a final step, it is useful to
plot the dB gain and phase of the following loop-gain
transfer function and check the obtained phase margin. A
phase margin of at least 45° is recommended:
where the sampling effect quality factor is:
Q
KD
C
S
=
××−−
[]
1
105π (().)
Gs
s
Qf
s
f
S
cSW
SW
()=
+
××
+
×
()
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
1
1
2
2
π
π
Gs
Rg
R
Lf
Ks D
LOOP
LOAD MC
LOAD
SW
()
()
=
×
+
×
××−
()
−11005
12
12
.
(/ )
(/ )
⎡
⎣
⎤
⎦
⎡
⎣
⎢
⎤
⎦
⎥
×
+×
+×
sf
sf
zMOD
pMOD
π
π
××
+×
+××+×
(/ )
(/ )(/ )
12
12 12
sf
sf sf
zEA
pEA pdEA
π
ππ
××
××gRoV
V
G
mEA
REFIN
OUT
S
(
C
Rf
F
CzMOD
=
××
1
2π
C
fR
C
pMOD C
=
××
1
2π
R
V
V
f
gG f
C
OUT
FB
C
mEA MOD fc zMOD
=×
××
()
GgR
f
f
EA fc mEA C
zMOD
C
()
=××
GG
f
f
MOD fc MOD dc
pMOD
zMOD
() ( )
=×
C
Rf
F
CzMOD
=
××
1
2π
C
fR
C
pMOD C
=
××
1
2π
R
V
gV G
C
OUT
mEA REFIN MOD fc
=
××
()
GgR
GG
f
f
EA fc mEA C
MOD fc MOD dc
pMOD
C
()
() ( )
=×
=×
GG
V
V
EA fc MOD fc
REFIN
OUT
() ()
××=1
ff
f
pMOD C
SW
<< ≤
5