Datasheet

MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-I
Q
, PMICs with Dynamic
Voltage Management for Mobile Applications
32
Voltage Monitors, Reset,
and Undervoltage-Lockout Functions
Undervoltage and Overvoltage Lockout
When the V
IN
is below V
UVLO
(typically 2.35V), the
MAX8660/MAX8661 enter its undervoltage-lockout
mode (UVLO). UVLO forces the device to a dormant
state. In UVLO, the input current is very low (1.5µA)
and all regulators are off. RSO and LBO are forced low
when the input voltage is between 1V (typ) and V
UVLO
.
The I
2
C does not function in UVLO, and the I
2
C register
contents are reset in UVLO.
When the input voltage is above V
OVLO
(typically 6.35V)
the MAX8660/MAX8661 enter overvoltage-lockout mode
(OVLO). OVLO mode protects the MAX8660/
MAX8661 from high-voltage stress. In OVLO, the input
current is 25µA and all regulators are off. RSO is held
low, the I
2
C does not function, and register contents are
reset in OVLO. LBO continues to function in OVLO; how-
ever, since LBO is typically pulled up to V8
( VCC_BBATT ), LBO appears to go low in OVLO because
V8 is disabled. Alternatively, LBO may be pulled up to IN.
Reset Output (RSO) and MR Input
RSO is an open-drain reset output. As shown in Figure
1, RSO typically connects to the nRESET input of the
applications processor and is pulled up to V8
( VCC_BBATT ). A low on nRESET causes the processor
to enter its reset state.
RSO is forced low when one or more of the following
conditions occur:
• MR is low.
• V8 is below V
RSOTH
(2.2V falling typ).
•V
IN
is below V
UVLO
(2.35V typ).
•V
IN
is above V
OVLO
(6.35V typ).
RSO is high impedance when all of the following condi-
tions are satisfied:
• MR is high.
• V8 is above V
RSOTH
(2.35V rising typ).
•V
UVLO
< V
IN
< V
OVLO
.
• The RSO deassert delay (t
VBHRSTH
= 24ms typ) has
expired.
When RSO goes low, the MAX8660/MAX8661 I
2
C regis-
ters are reset to their default values.
If the MR feature is not required, connect MR high. If
the RSO feature is not required, connect RSO low.
Low-Battery Detector (LBO, LBF, LBR)
LBO is an open-drain output that typically connects to the
nBATT_FAULT input of the applications processor to indi-
cate that the battery has been removed or discharged
(Figure 1). LBO is typically pulled up to V8 ( VCC_BBATT ).
LBR and LBF monitor the input voltage (usually a bat-
tery) and trigger the LBO output (Figure 7). The truth
table in Figure 7 shows that LBO is high impedance
when the voltage from LBR to AGND (V
LBR
) exceeds
the low-battery rising threshold (V
LBRTH
= 1.25V typ).
LBO is low when the voltage from LBF to AGND (V
LBF
)
falls below the low-battery falling threshold (V
LBFTH
=
1.20V typ). On power-up, the LBR threshold must be
exceeded before LBO deasserts.
Connecting LBF to LBR and to a two-resistor voltage-
divider sets a 50mV hysteresis referred to LBF (hystere-
sis at the battery voltage is scaled up by the resistor
value), connecting LBF and LBR separately to a three-
resistor voltage-divider (Figure 7) allows the falling
threshold and rising threshold to be set separately
(achieving larger hysteresis). The Figure 7 resistor val-
ues are selected as a function of the desired falling
(V
LBOF
) and rising (V
LBOR
) thresholds as follows:
First, select R3 in the 100kΩ to 1MΩ range:
RRx
V
V
x
V
V
RRx
VxV
VxV
LBOR
LBRTH
LBFTH
LBOF
LBFTH LBOR
LBRTH LBOF
13 1
23 1
=−
⎛
⎝
⎜
⎞
⎠
⎟
=−
⎛
⎝
⎜
⎞
⎠
⎟
MAX8660
MAX8661
V
LBFTH
1.200V
V
LBRTH
1.250V
SQ
R
LBR
LBF
IN
R3
R2
R1
AGND
LBO
+
V8
(VCC_BBATT
)
V
LBF
< V
LBFTH
V
LBR
< V
LBRTH
0
LBF LBR
TRUTH TABLE
LBO
V
LBF
< V
LBFTH
V
LBR
> V
LBRTH
0
V
LBF
> V
LBFTH
V
LBR
< V
LBRTH
HOLD
V
LBF
> V
LBFTH
V
LBR
> V
LBRTH
1
Figure 7. Low-Battery Detector Functional Diagram