Datasheet

MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-I
Q
, PMICs with Dynamic
Voltage Management for Mobile Applications
26
MAXIM MARVELL DESCRIPTION
EN34 PWR_EN
Active-High Enable Signal for Processor Core Power. The applications processor drives this
PWR_EN signal high to exit sleep mode. The processor’s PWR_EN logic is powered by the
MAX8660/MAX8661 “always on” V8 (VCC_BBATT) regulator during sleep mode.
EN1, EN2, EN5 SYS_EN
Active-High Enable Signal for Peripheral Power Supplies. The applications processor drives
this SYS_EN signal high to enter run mode.
RSO nRESET
Active-Low Reset. The MAX8660/MAX8661 drive this signal low to reset the processor.
When RSO goes low, the MAX8660/MAX8661 I
2
C registers are reset to their default values.
LBO nBATT_FAULT
Active-Low Battery Fault. The MAX8660/MAX8661 drive this signal low to signal the
processor that the battery has been removed or discharged.
SDA
GPIO33
PWR_SDA
I
2
C Serial-Data Input/Output. The MAX8660/MAX8861 SDA generally connects to both the
Marvell PXA3xx processor’s standard I
2
C data line (GPIO33) and its dedicated power I
2
C
data line. This connection operates as an I
2
C multimaster system with the
MAX8660/MAX8661 accepting commands from both the standard I
2
C and the power I
2
C.
SCL
GPIO32
PWR_SCL
I
2
C Serial Clock. The MAX8660/MAX8661 SCL generally connects to both the Marvell
PXA3xx processor’s standard I
2
C clock line (GPIO32) and its dedicated power I
2
C clock
line. This connection operates as an I
2
C multimaster system with the MAX8660/MAX8661
accepting commands from both the standard I
2
C and the power I
2
C.
Table 2. Maxim and Marvell PXA3xx Digital Signal Terminology
Step-Down DC-DC Converters
(REG1–REG4)
REG1 (VCC_IO) Step-Down DC-DC Converter
(MAX8660 Only)
REG1 is a high-efficiency (REG1 + REG8 I
Q
= 40µA)
2MHz current-mode step-down converter that outputs
up to 1200mA with efficiency up to 96% (see the
Typical Operating Characteristics ). The output voltage
(V1) is selected with the SET1 input as shown in Table
3. The REG1 output voltage selection is latched at the
end of the REG1 soft-start period. Changes in SET1
after the startup period have no effect.
EN1 is a dedicated enable input for REG1. Drive EN1
high to enable REG1 or drive EN1 low to disable REG1.
EN1 has hysteresis so that an RC may be used to
implement manual sequencing with respect to other
inputs. In systems based on Marvell PXA3xx proces-
sors, EN1, EN2, and EN5 are typically connected to
SYS_EN (Table 2).
The REG1 step-down regulator operates in either nor-
mal or forced-PWM mode. See the REG1–REG4 Step-
Down DC-DC Converter Operating Modes
section for
more information.
REG1 has an on-chip synchronous rectifier. See the
REG1–REG4 Synchronous Rectification section for
more information.
The REG1 regulator allows 100% duty-cycle operation.
See the REG1/REG2 100% Duty-Cycle Operation
(Dropout) section for more information.
REG2 (VCC_IO, VCC_MEM)
Step-Down DC-DC Converters
REG2 is a high-efficiency (REG2 + REG8 I
Q
= 40µA)
2MHz current-mode step-down DC-DC converter that
outputs up to 900mA with efficiency up to 96%. The out-
put voltage is selected with the SET2 input as shown in
Table 4. The REG2 output voltage selection is latched
at the end of the REG2 soft-start period. Changes in
SET2 after the startup period have no effect.
SET1*
MAX8660/
MAX8660B: V1 (V)
MAX8660A: V1 (V)
IN 3.3 2.5
UNCONNECTED 3.0 2.0
GROUND 2.85 1.8
Table 3. SET1 Logic
* SET1 is latched after REG1 startup.
SET2*
M A X8 6 6 0 /M A X8 6 6 0 B /
M A X8 6 6 1 : V2 ( V)
M A X8 6 6 0 A : V2 ( V)
IN 3.3 2.5
UNCONNECTED 2.5 2.0
GROUND 1.8 1.8
Table 4. SET2 Logic
* SET2 is latched after REG2 startup.