Datasheet

MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-I
Q
, PMICs with Dynamic
Voltage Management for Mobile Applications
19
Pin Description
PIN
MAX8660 MAX8661
NAME FUNCTION
1 1 IN5
REG5 Power Input. Connect IN5 to IN to ensure V5 rises first to meet the Marvell PXA3xx
processor’s sequencing requirements. If adherence to this sequencing specification is not
required, connect IN5 to V1, V2, or another supply between 2.35V and V
IN
. See the Linear
Regulators (REG5–REG8) section for more information.
— 2 V5
REG5 Linear-Regulator Output. V5 defaults to 1.8V and is adjustable from 1.7V to 2.0V through
the serial interface. The input to the V5 regulator is IN5. Use V5 to power VCC_MVT, VCC_BG,
VCC_OSC13M, and VCC_PLL on Marvell PXA3xx processors. V5 is internally pulled to AGND
through 2kΩ when REG5 is shut down.
3 3 PV4
REG4 Power Input. Connect a 4.7µF ceramic capacitor from PV4 to PG4. All PV pins and IN must
be connected together externally.
4 4 LX4
REG4 Switching Node. Connect LX4 to the REG4 inductor. LX4 is high impedance when REG4 is
shut down.
5 5 PG4
RE G 4 P ow er G r ound . C onnect P G 1, P G 2, P G 3, P G 4, and AG N D tog ether . Refer to the M AX 8660 E V
ki t data sheet for more information.
6 6 SET2
REG2 Voltage Select Input. SET2 is a tri-level logic input. Connect SET2 to select the V2 output
voltage as detailed in Table 4. The REG2 output voltage selected by SET2 is latched at the end of
the REG2 soft-start period. Changes to SET2 after the startup period have no effect.
7 7 V6
REG6 Linear-Regulator Output. REG6 is activated and programmed through the serial interface to
output from 1.8V to 3.3V in 0.1V steps. REG6 is off by default. V6 is internally pulled to AGND
through 350Ω when REG6 is shut down. V6 optionally powers VCC_CARD1 on Marvell PXA3xx
processors.
8 — IN67
REG6 and REG7 Power Input. IN67 is typically connected to IN. IN67 can also be connected to
any supply between 2.35V to V
IN
.
— 8 IN6
REG6 Power Input. IN6 is typically connected to IN. IN6 can also be connected to any supply
between 2.35V to V
IN
.
9 — V7
REG7 Linear-Regulator Output. REG7 is activated and programmed through the serial interface to
output from 1.8V to 3.3V in 0.1V steps. REG7 is off by default. V7 is internally pulled to AGND
through 350Ω when REG7 is shut down. V7 optionally powers VCC_CARD2 on Marvell PXA3xx
processors.
— 9 N.C. No Internal Connection
10 10 V2
REG2 Voltage Sense Input. Connect V2 directly to the REG2 output voltage. The output voltage of
REG2 is selected by SET2. V2 is internally pulled to AGND through 650Ω when REG2 is shut
down. V2 powers VCC_MEM on Marvell PXA3xx processors.
11 11 SCL Serial-Clock Input. See the I
2
C Interface section.
12 12 SDA Serial-Data Input. See the I
2
C Interface section.
13 13 LBO
Low-Battery Output. LBO is an open-drain output that pulls low when LBF is below its threshold.
LBO typically connects to the nBATT_FAULT input of the applications processor to indicate that
the battery has been removed or discharged.
14 14 PV2
REG2 Power Input. Connect a 4.7µF ceramic capacitor from PV2 to PG2. All PV pins and IN must
be connected together externally.
15 15 LX2
REG2 Switching Node. Connect LX2 to the REG2 inductor. LX2 is high impedance when REG2 is
shut down.