Datasheet

MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-I
Q
, PMICs with Dynamic
Voltage Management for Mobile Applications
28
converters to maintain regulation until the input voltage
falls below the desired output voltage plus the dropout
voltage specification of the converter. During 100%
duty-cycle operation, the high-side p-channel MOSFET
turns on constantly, connecting the input to the output
through the inductor. The dropout voltage (V
DO
) is cal-
culated as follows:
V
DO
= I
LOAD
(R
P
+ R
L
)
where:
R
P
= p-channel power switch R
DS(ON)
R
L
= external inductor ESR
The REG1 dropout voltage is 200mV with a 1200mA
load (with inductor resistance = 50mΩ). The REG2
dropout voltage is 225mV with a 900mA load (with
inductor resistance = 67mΩ).
Linear Regulators (REG5–REG8)
REG5 (VCC_MVT, VCC_BG,
VCC_OSC13M, VCC_PLL)
REG5 is a linear regulator with an I
2
C-adjustable output
voltage from 1.700V to 2.000V in 25mV increments
(REG5 + REG8 I
Q
= 55µA). The default REG5 voltage is
1.8V. REG5 delivers up to 200mA. See the I
2
C Interface
section for details on how to adjust the output voltage.
The power input for the REG5 linear regulator is IN5. The
IN5 input voltage range extends down to 2.35V. Note that
in the Marvell PXA3xx specification, VCC_MVT is enabled
by
SYS_EN (along with V1 and V2), but must not rise after
V1 (
VCC_IO ) or V2 ( VCC_MEM ). This requirement dic-
tates that IN5 be connected to IN and not V1 or V2.
EN5 is a dedicated enable input for REG5. Drive EN5
high to enable REG5. Drive EN5 low to disable REG5.
EN5 has hysteresis so that an RC may be used to imple-
ment manual sequencing with respect to other inputs. In
systems with Marvell PXA3xx processors, EN1, EN2,
and EN5 are typically connected to
SYS_EN (Table 2).
REG6/REG7 (VCC_CARD1, VCC_CARD2)
The REG6/REG7 linear regulators supply up to 500mA
each (REG6 or REG 7 + REG8 I
Q
= 85µA). The output
voltages, V6 and V7, are programmable through the ser-
ial interface from 1.8V to 3.3V in 0.1V steps (Table 13).
See the
I
2
C Interface section for details on changing the
V6 or V7 voltage. On the MAX8660, the combined
power input for the REG6 and REG7 linear regulators is
IN67. On the MAX8661, IN6 is the power input for REG6
(REG7 is not available on the MAX8661).
REG6 and REG7 are disabled by default and must be
enabled using the I
2
C serial interface. REG6 and REG7
have independent enable bits in the OVER2 register:
EN6 and EN7 (Table 9). To enable the regulators, set
the corresponding enable bit.
REG8 (VCC_BBATT) Always-On Regulator
The output of REG8 (V8) is always active when the input
voltage (V
IN
) is above the undervoltage-lockout threshold
of 2.55V (max) and below the overvoltage-lockout thresh-
old of 6.0V (min). The REG8 linear regulator is supplied
from IN and its output regulates to 3.3V and supplies up
to 30mA. The internal REG8 pass element is 12Ω in
dropout, providing a 180mV dropout voltage with a 15mA
output current. Connect V8 to VCC_BBATT for applica-
tions that use Marvell PXA3xx processors. The RSO out-
put goes low if V8 is less than 2.2V (falling typ).
Ramp-Rate Control (RAMP)
REG1 and REG2 have a fixed soft-start ramp that elimi-
nates input current spikes when they are enabled; 200µs
after being enabled, REG1 and REG2 linearly ramp from
0V to the set output voltage in 450µs. When these regu-
lators are disabled, the output voltage decays at a rate
determined by the output capacitance, internal 650Ω
discharge resistance, and the external load.
The REG3 and REG4 output voltage have a variable lin-
ear ramp rate that is set by a resistor connected from
RAMP to AGND (R
RAMP
). This resistor controls the out-
put-voltage ramp rate during soft-start and a positive
voltage change (i.e., 1.0V to 1.4V). The negative volt-
age change (i.e., 1.4V to 1.0V) is controlled in forced-
PWM mode, and when the ARD bit is set in normal
mode (Table 9). Figure 4 shows the relationship
RAMP RATES vs. RAMP-RATE RESISTOR
R
RAMP
(kΩ)
RAMP RATE (mV/µs)
0
2
4
6
8
10
12
10 100 1000
REG3/4/5 DCRR
REG3/4 SSRR TO:
1V
1.4V
1.8V
Figure 4. Soft-Start and Voltage-Change Ramp Rates
REG REG SOFT START RAMP RATE SSRR
SSRR
mV
s
34/():−
⎡
µ
⎣⎣
⎢
⎤
⎦
⎥
=
×
[]
×× Ω
[]
14
0 0014848 2 2
.
.(.(
VV
Rk
OUT
RAMP
+++
−
13 5 9
345
.) )
//REG REG REG DYNAMIC CHANGE RAMP R
AATE DCRR
DCRR
mV
sx R
RAM
()
(. (µ
⎡
⎣
⎢
⎤
⎦
⎥
=
×
12500
822
PP
kΩ
[]
++13 5 9.) )